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  pWp//&// ?>?   ??        // {v >>J\yy7!!JanFebMarAprMayJunJulAugSepOctNovDecOOOOOO%d - MSign crashed!Traceback (recent calls first)=== CONTEXT ===bus fault:during exception stackingduring exception unstackingduring inst fetchduring data fetchwhile accessing 0x%08xusage fault:no coprocessorundefined instructioninvalid isa stateinvalid exception returnunaligned load/storedivide by 0unknownmemory protection fault:from ISR %dcorrupted RTOS statefrom thread %sTraceback for servicerTraceback for screenTraceback for dbgtimsrv pending requests:NoneChangeTempChangeTempMultiRxTimeDumpLogOutRefreshGrabberSleepModeResetSyncsrv ping waitingrebooting:interrupt handlerassert failedscreen refresh watchdogMemManage (xn fail)UsageFaultBusFaultRxNoHandlestack over %ssrvcscreendbtimIDLEnowa second%s ago%d %s agosecondsin %sin %d %sa minuteminutesan hourhoursyesterdaytomorrowa daydaysloadingno updates yetest. delivery %02d:%02dprinter off%02d%% done; ly %d/%d (%d.%02d mm)doneest. finishedUPD WAITUPD ESIMGUPD FAILUPD CFAILUPD EPS%02dUPD P%04dUPD WESPUPD ESCT%04dUPD EWRTMSIGN V4.2-broken-eap-sm-reinit-c9fb179STM OKBLOAD ESP OKinvalid selected for ::get()yesconnected: ip: %d.%d.%d.%dgw: %d.%d.%d.%dnobl rev: stm ver: V4.2-broken-eap-sm-reinit-c9fb179esp ver: esp timeoutout of bounds put%+dnextheldscore%dlinesGAME OVERhold SELECT to restart%02d:00no data%02d%+03dm+0%100%feels like (C)temp (C)wind (km/h)wind gusts (km/h)precip (minutely, mm/h)precip (hourly, mm/h)> bad spacetest panictest nonfatalESP WAITUPD NONEUPD INITESP CRASH sys sys uiui certcert ui errerr%d.%d %d %d%d %s, %s %d%02d:%02d <0.1 mm/hr%d.%d mm/hr%d mm/hr%d cm/hr%d mm%d.%d cm%d cm%d%%full rangeCalibrate ADCMove stick overLeave still[PWR] to continue[MENU] to resetsavingfailed to save calibrationx %04d y %04d[PWR] to save[MENU] to restarttruefalsependreq: %05d mstime: ; ping? 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K/X /home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/libc/usr/local/lib/gcc/arm-none-eabi/13.3.1/includemem.cstddef.hstdint.hstdint-gcc.hUdX  U.y < -Y  -!   !   ;<1#.  s.<(x JK < -g   !   !   ;x  / / - ! -4 00 0."  .X        .   /home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/libc/usr/local/lib/gcc/arm-none-eabi/13.3.1/includestr.cstddef.hstdint.hstdint-gcc.hTY    .! .  0V1! .( !/!.44#+1!w !2+1CAN_F5R2_FB7 CAN_F5R2_FB7_MskEXTI_EMR_EM20 EXTI_EMR_MR20RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_MskRCC_CSR_PADRSTF RCC_CSR_PINRSTFUSART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_MskFSMC_BTR3_BUSTURN_Pos (16U)MSN_CRASH_DECODE_H MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)ETH_MACHTLR_HTL ETH_MACHTLR_HTL_MskCAN_F11R1_FB2 CAN_F11R1_FB2_Msk__ARM_FEATURE_SAT 1IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_MskSYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)IWDG_KR_KEY IWDG_KR_KEY_MskportYIELD() { portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; __asm volatile ( "dsb" ::: "memory" ); __asm volatile ( "isb" ); }CAN_F4R1_FB2_Pos (2U)CAN_TSR_TME0_Pos (26U)CAN_F7R1_FB24_Pos (24U)GPIO_BSRR_BR_10 GPIO_BSRR_BR10CAN_FA1R_FACT19_Pos (19U)_ZN5crash4srvd21ServicerDebugAccessor27get_debug_servicer_did_pingEvLL_TIM_TRGO_RESET 0x00000000UCAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0CAN_F11R1_FB25 CAN_F11R1_FB25_MskADC_CCR_ADCPRE_Pos (16U)ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)_STL_ITERATOR_BASE_FUNCS_H 1RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)SDIO_ICR_CTIMEOUTC_Pos (2U)FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)_GLIBCXX_DEBUG_ASSERTIONS_H 1ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_MskTIM_EGR_UG TIM_EGR_UG_MskFSMC_PIO4_IOHIZ4_Pos (24U)__EXCEPTION_H 1__ARM_FEATURE_QBIT 1USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)CAN_F3R2_FB2_Pos (2U)CAN_F2R1_FB13 CAN_F2R1_FB13_MskCAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)__thumb__ 1USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_MskSDIO_STA_DATAEND_Pos (8U)ADC_CR1_DISCNUM_Pos (13U)ETH_MACMIIAR_MR_Pos (6U)CAN_MCR_ABOM_Pos (6U)EXTI_EMR_MR10_Pos (10U)SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_MskADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)FLASH_CR_STRT FLASH_CR_STRT_MskADC_JDR3_JDATA ADC_JDR3_JDATA_MskCAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)portCLEAN_UP_TCB(pxTCB) ( void ) pxTCBLL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)TIM_EGR_CC1G_Pos (1U)__cpp_aggregate_paren_init 201902LFSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)GPIO_PUPDR_PUPD4 0x00000300U_POSIX_C_SOURCEUSB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)CAN_F10R1_FB11_Pos (11U)USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_MskSDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)CAN_RDT1R_DLC_Pos (0U)RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)GPIO_IDR_ID8 0x00000100UCAN_F10R2_FB4 CAN_F10R2_FB4_MskEXTI_RTSR_TR21 EXTI_RTSR_TR21_MskFSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)RCC_CFGR_MCO1PRE_Pos (24U)GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)traceTASK_NOTIFY_TAKE(uxIndexToWait) CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_MskRTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_MskCAN_F9R1_FB28_Pos (28U)__cpp_constexpr 202002L_GLIBCXX_USE_C99_INTTYPES_TR1 1ETH_MACFFR_PCF_ForwardAll_Pos (7U)CAN_FA1R_FACT9_Pos (9U)MODERADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)_GLIBCXX_HAVE_FREXPF 1FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_MskUBaseType_tETH_MACFCR_PLT_Pos (4U)USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_MskRTC_TAFCR_TSINSEL_Pos (17U)tmpregCAN_F13R1_FB5 CAN_F13R1_FB5_MskETH_MACA3HR_MACA3H_Pos (0U)RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)__PMT(args) argsFSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_MskRCC_CSR_SFTRSTF_Pos (28U)USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_MskDMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_MskCAN_F12R1_FB21_Pos (21U)USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_MskUSB_OTG_DIEPINT_BERR_Pos (12U)CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)TIM_SR_CC4OF_Pos (12U)ADC_SQR1_SQ16 ADC_SQR1_SQ16_MskRTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)CAN_F1R1_FB9 CAN_F1R1_FB9_MskETH_DMAOMR_RTC ETH_DMAOMR_RTC_MskADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)GPIO_AFRL_AFSEL4_0 0x00010000UCAN_F8R2_FB14_Pos (14U)APSR_Z_Pos 30UETH_DMASR_MMCS ETH_DMASR_MMCS_MskFSMC_BCR1_MUXEN_Pos (1U)__cpp_constexpr_in_decltype 201711LUSB_OTG_BCNT_Pos (4U)FSMC_SR3_IFS FSMC_SR3_IFS_MskDBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_MskDMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)FSMC_BCR2_MTYP_Pos (2U)SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)CAN_F1R2_FB5_Pos (5U)I2C_SR2_MSL I2C_SR2_MSL_MskFSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)CAN_F4R1_FB0 CAN_F4R1_FB0_MskFSMC_SR3_FEMPT FSMC_SR3_FEMPT_MskUSB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_MskCAN_F3R2_FB0 CAN_F3R2_FB0_MskRTC_BKP19R RTC_BKP19R_MskSVCall_IRQnGPIO_MODER_MODE2_0 0x00000010UUSB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)FSMC_BCR3_WREN FSMC_BCR3_WREN_MskCAN_FM1R_FBM17 CAN_FM1R_FBM17_MskGPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)EXTI_IMR_MR6 EXTI_IMR_MR6_MskCAN_F12R2_FB7 CAN_F12R2_FB7_MskSYSCFG_EXTICR4_EXTI12_PC 0x00000002U__STATIC_FORCEINLINE __attribute__((always_inline)) static inlineUINT_LEAST32_MAXCAN_F0R2_FB19 CAN_F0R2_FB19_MskCAN_F13R2_FB27 CAN_F13R2_FB27_MskETH_DMA_BASE (ETH_BASE + 0x1000UL)LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1RCC_APB1ENR_SPI2EN_Pos (14U)DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)CAN_F0R1_FB21_Pos (21U)LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1)CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)TIM_CCER_CC3NP_Pos (11U)GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)CAN_F2R2_FB2 CAN_F2R2_FB2_Msk__WCHAR_T__ LL_DMA_PDATAALIGN_BYTE 0x00000000UUSB_OTG_GRSTCTL_FCRST_Pos (2U)I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)TPI ((TPI_Type *) TPI_BASE )CAN_MCR_RFLM_Pos (3U)IABRFSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)I2C_CCR_CCR_Pos (0U)EXTI_EMR_MR2_Pos (2U)USB_OTG_PCGCR_STPPCLK_Pos (0U)__exported __attribute__((__visibility__("default")))I2C_SR1_BTF_Pos (2U)RTC_BKP13R RTC_BKP13R_MskFSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)portTICK_TYPE_IS_ATOMIC 1SDIO_RESPCMD_RESPCMD_Pos (0U)PWR_CR_LPDS PWR_CR_LPDS_MskCAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)EXTI_IMR_MR12 EXTI_IMR_MR12_MskCAN_TI0R_RTR_Pos (1U)FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK)CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)WWDG_CFR_W6 WWDG_CFR_W_6USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)CAN_FM1R_FBM14_Pos (14U)ETH_DMASR_TPS_Pos (20U)EXTI_FTSR_TR13 EXTI_FTSR_TR13_MskportFLOAT floatEXTI_PR_PR18_Pos (18U)FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)_GLIBCXX_MOVE3(_Tp,_Up,_Vp) std::move(_Tp, _Up, _Vp)CAN_F3R1_FB3_Pos (3U)RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)GPIO_PUPDR_PUPD14_0 0x10000000UEXTI_PR_PR0_Pos (0U)SDIO_DCTRL_DMAEN_Pos (3U)CAN_F2R1_FB31_Pos (31U)CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)ETH_MACA1HR_MBC_LBits7_0 0x01000000UCAN_F13R2_FB11_Pos (11U)FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)__fastcall __attribute__((__fastcall__))FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CTUSB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_MskI2C_CCR_DUTY I2C_CCR_DUTY_MskCAN_RDH0R_DATA5_Pos (8U)RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_MskDMA_HIFCR_CDMEIF6_Pos (18U)CAN_F2R2_FB31 CAN_F2R2_FB31_MskUSB_OTG_HCINT_DTERR_Pos (10U)pdTASK_CODE TaskFunction_tMPU_WRAPPERS_H CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk_REENT_ASCTIME_SIZE 26_GLIBCXX_HAVE_COMPLEX_H 1CAN_F8R2_FB1_Pos (1U)__EXPORT USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)CAN_F6R1_FB2_Pos (2U)TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)CAN_F4R1_FB18_Pos (18U)RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_MskDWT_LSUCNT_LSUCNT_Msk (0xFFUL )CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)FSMC_BCR4_BURSTEN_Pos (8U)RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)EXTI_EMR_MR17_Pos (17U)LL_GPIO_AF_2 (0x0000002U)EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)TIM_CCR2_CCR2_Pos (0U)FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_MskDMA_LIFCR_CFEIF1_Pos (6U)NVIC_DisableIRQ __NVIC_DisableIRQRTC_BKP1R_Pos (0U)ADC_CR1_AWDIE ADC_CR1_AWDIE_MskEXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)TIM11 ((TIM_TypeDef *) TIM11_BASE)EspNormal_GLIBCXX_MOVE(__val) std::move(__val)CAN_F2R1_FB20 CAN_F2R1_FB20_MskETH_PTPTSLR_STSS_Pos (0U)_Bool boolCAN_F5R2_FB27 CAN_F5R2_FB27_MskSDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_MskRNG ((RNG_TypeDef *) RNG_BASE)DAC ((DAC_TypeDef *) DAC_BASE)USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_MskI2C_CR1_START_Pos (8U)FSMC_SR2_IRS FSMC_SR2_IRS_MskDMA_LISR_HTIF3 DMA_LISR_HTIF3_MskINCLUDE_vTaskSuspend 1__NVIC_PRIO_BITS 4UFSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk__ARM_FEATURE_UNALIGNED 1SYSCFG_EXTICR1_EXTI1_PF 0x00000050UCAN_F1R2_FB11_Pos (11U)ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)__ORDER_PDP_ENDIAN__ 3412FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)FSMC_SR3_IREN_Pos (3U)__UHQ_FBIT__ 16OPTCRCAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)CAN_F12R2_FB5_Pos (5U)SDIO_MASK_RXFIFOEIE_Pos (19U)SYSCFG_EXTICR3_EXTI10_PG 0x00000600UITM_TCR_TraceBusID_Pos 16UCAN_FA1R_FACT15_Pos (15U)CAN_F8R2_FB9_Pos (9U)CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_MskTIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)EXTI_SWIER_SWIER3_Pos (3U)__CLZ (uint8_t)__builtin_clzCAN_F0R1_FB2_Pos (2U)__predict_false(exp) __builtin_expect((exp), 0)TIM_EGR_COMG TIM_EGR_COMG_MskCAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)UART4 ((USART_TypeDef *) UART4_BASE)FSMC_SR2_IRS_Pos (0U)EXTI_PR_PR10 EXTI_PR_PR10_MskCAN_F1R2_FB18 CAN_F1R2_FB18_MskCAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)CAN_F10R1_FB3 CAN_F10R1_FB3_MskADC_SMPR2_SMP1_Pos (3U)FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)CAN_F3R2_FB21_Pos (21U)RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_MskEXTI_FTSR_TR5_Pos (5U)GPIO_IDR_ID10 0x00000400URTC_BKP2R RTC_BKP2R_MskFSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_MskETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)_WCHAR_T_DEFINED_ SYSCFG_EXTICR1_EXTI3_PI 0x00008000UFSMC_PMEM4_MEMHIZ4_Pos (24U)FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13ENADC_CR1_JAUTO ADC_CR1_JAUTO_MskFSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)__cpp_raw_strings 200710LETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_MskADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)FLASH_SR_BSY FLASH_SR_BSY_Msk__INTMAX_TYPE__ long long intCAN_F13R1_FB28 CAN_F13R1_FB28_MskCAN_FS1R_FSC10_Pos (10U)RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_MskETH_PTPTSHR_STS_Pos (0U)ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_MskUSB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)ADC_DR_DATA ADC_DR_DATA_MskADC_SQR2_SQ7_Pos (0U)SYSCFG_EXTICR1_EXTI1_PD 0x00000030UTPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)CAN_F1R2_FB3_Pos (3U)_RAND48_MULT_0 (0xe66d)SYSCFG_EXTICR1_EXTI3_PF 0x00005000U_REENT_MP_FREELIST(ptr) ((ptr)->_freelist)LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)listSECOND_LIST_INTEGRITY_CHECK_VALUE __ACCUM_IBIT__ 16FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)GPIO_BSRR_BR_11 GPIO_BSRR_BR11SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_MskUSB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_MskETH_DMAOMR_TTC_24Bytes 0x00018000UCAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)_GLIBCXX_DARWIN_USE_64_BIT_INODE 1CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)CAN_FFA1R_FFA CAN_FFA1R_FFA_MskTPI_FIFO0_ETM0_Msk (0xFFUL )CAN_F12R1_FB17 CAN_F12R1_FB17_MskRCC_APB1ENR_TIM13EN_Pos (7U)RCC_AHB1RSTR_DMA1RST_Pos (21U)USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2configUSE_PORT_OPTIMISED_TASK_SELECTION 1__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2GPIO_MODER_MODE14_0 0x10000000UCAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)CAN_F5R2_FB22 CAN_F5R2_FB22_Msk__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)__INT_NUSB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)SYSCFG_EXTICR1_EXTI3_PC 0x00002000UFSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)FSMC_SR3_IFS_Pos (2U)CAN_F12R1_FB23 CAN_F12R1_FB23_MskCAN_F5R2_FB25_Pos (25U)__cpp_lib_shift 201806LSysTick_CTRL_ENABLE_Msk (1UL )TIM_EGR_CC2G TIM_EGR_CC2G_MskCAN_F11R1_FB19_Pos (19U)RTC_BKP0R RTC_BKP0R_MskGPIO_LCKR_LCK12 GPIO_LCKR_LCK12_MskSDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)RTC_TAFCR_ALARMOUTTYPE_Pos (18U)GPIO_BSRR_BS_3 GPIO_BSRR_BS3SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_MskUSB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)CAN_F4R1_FB29 CAN_F4R1_FB29_MskTIM_CCER_CC4NP TIM_CCER_CC4NP_MskCAN_F12R1_FB6 CAN_F12R1_FB6_MskCAN_FS1R_FSC10 CAN_FS1R_FSC10_MskUSART2 ((USART_TypeDef *) USART2_BASE)CAN_F13R2_FB5 CAN_F13R2_FB5_MskRCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)CAN_F6R2_FB26 CAN_F6R2_FB26_MskTPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)SPI_CR1_DFF_Pos (11U)CAN_F6R1_FB10 CAN_F6R1_FB10_MskCAN_RDH1R_DATA7_Pos (24U)GPIO_PUPDR_PUPD12_1 0x02000000USDIO_ICR_CMDSENTC_Pos (7U)FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)__LL_TIM_CALC_PULSE(__TIMCLK__,__PSC__,__DELAY__,__PULSE__) ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))USB_OTG_HCCHAR_LSDEV_Pos (17U)FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)ETH_MACMIIAR_PA_Pos (11U)SRAM1_BB_BASE 0x22000000ULCAN_F2R2_FB22 CAN_F2R2_FB22_MskDCMI_CR_CROP DCMI_CR_CROP_Msk__FPU_USED 0URCC_CIR_PLLI2SRDYC_Pos (21U)RCC_CIR_LSIRDYC_Pos (16U)PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)GPIO_LCKR_LCK9_Pos (9U)CAN_F5R1_FB23 CAN_F5R1_FB23_MskCAN_F13R1_FB29_Pos (29U)EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)_GLIBCXX_MANGLE_SIZE_T jLL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)ETH_DMAOMR_TTC_256Bytes 0x0000C000UETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)USB_OTG_HCINTMSK_XFRCM_Pos (0U)I2C_SR2_BUSY_Pos (1U)USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_MskDMA_LISR_TCIF1 DMA_LISR_TCIF1_MskEXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)CAN_F6R1_FB15 CAN_F6R1_FB15_MskTIM_DCR_DBL TIM_DCR_DBL_MskCAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)SYSCFG_EXTICR2_EXTI7_PB 0x00001000UUINT64_C(c) __UINT64_C(c)SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)ETH_MACA2HR_MBC_HBits15_8 0x20000000UEXTI_EMR_MR10 EXTI_EMR_MR10_MskPWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)__FLT64_NORM_MAX__ 1.7976931348623157e+308F64CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)CAN_F12R1_FB6_Pos (6U)CAN_TDH1R_DATA4_Pos (0U)USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)listGET_OWNER_OF_HEAD_ENTRY(pxList) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)GPIO_ODR_OD9 0x00000200U__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)RTC_TSDR_DU_Pos (0U)CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)ETH_PTPTSSR_TSSIPV4FE_Pos (13U)LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UCAN_F11R2_FB8 CAN_F11R2_FB8_MskRCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_MskUSB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_MskCAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)CAN_F12R2_FB15_Pos (15U)CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)CAN_F10R2_FB22_Pos (22U)__WEAK __attribute__((weak))_GLIBCXX_ALGORITHM 1ADC_CR1_SCAN ADC_CR1_SCAN_MskUSB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_MskLL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)RCC_APB2LPENR_TIM9LPEN_Pos (16U)ADC_HTR_HT_Pos (0U)FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)USART_GTPR_PSC USART_GTPR_PSC_MskRCC_AHB1RSTR_GPIODRST_Pos (3U)PreemptPriorityETH_DMAIER_ETIE ETH_DMAIER_ETIE_MskDAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)GPIO_PUPDR_PUPD15_1 0x80000000UUSB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)CAN_F1R1_FB29_Pos (29U)TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)ETH_DMASR_ETS ETH_DMASR_ETS_MskLL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_MskRCC_CR_HSICAL_Pos (8U)GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0__size_t GPIO_BSRR_BR9 0x02000000ULL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK)TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_MskUSB_OTG_GLOBAL_BASE 0x000ULSCB_CPUID_REVISION_Pos 0URCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_MskLL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK)USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)CAN_MSR_SLAK_Pos (1U)FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)CAN_F0R2_FB21_Pos (21U)SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)NVIC_STIR_INTID_Msk (0x1FFUL )SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)__NOP() __ASM volatile ("nop")ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_MskUSB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_MskCAN_F1R1_FB4_Pos (4U)FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)portTICK_TYPE_ENTER_CRITICAL() SysTick_VAL_CURRENT_Pos 0UUSART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)TIMx_OR_RMP_MASK 0x0000FFFFU__cpp_enumerator_attributes 201411LCAN_F7R2_FB20 CAN_F7R2_FB20_MskFSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)GPIO_BSRR_BS5 0x00000020U__swappable_detailsFSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_MskDAC_CR_TEN2_Pos (18U)DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)EXTI_RTSR_TR13 EXTI_RTSR_TR13_MskGPIO_MODER_MODER8_Pos (16U)LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGENpcQueueGetQueueName pcQueueGetNameGPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_MskRNG_CR_RNGEN RNG_CR_RNGEN_MskCAN_TDT1R_TGT_Pos (8U)FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_MskETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_MskCAN_F0R2_FB15_Pos (15U)USB_OTG_DOEPMSK_STUPM_Pos (3U)_PSTL_VERSION_MAJOR (_PSTL_VERSION / 1000)USB_OTG_FIFO_SIZE 0x1000ULCAN_F13R1_FB15_Pos (15U)RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)_GLIBCXX_STATIC_TZDATA 1INT16_MIN (-INT16_MAX - 1)CAN_F4R1_FB3_Pos (3U)RTC_ALRMBR_DU_Pos (24U)DMA_HISR_FEIF4_Pos (0U)LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_MskETH_DMAIER_RIE ETH_DMAIER_RIE_MskSCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)calibrateETH_MACA1HR_AE ETH_MACA1HR_AE_MskCAN_IER_TMEIE CAN_IER_TMEIE_MskBKP14RCAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)ETH_MACFFR_PM_Pos (0U)__have_longlong64 1USB_OTG_GINTSTS_CIDSCHG_Pos (28U)USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)__LACCUM_FBIT__ 31is_rtos_runningSPI2 ((SPI_TypeDef *) SPI2_BASE)CAN_F3R2_FB11 CAN_F3R2_FB11_MskUSB_OTG_HCINTMSK_BBERRM_Pos (8U)RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msktask_bufferCAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)GPIO_ODR_OD7 0x00000080UCAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)DMA_LISR_TEIF0_Pos (3U)CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)CAN_F9R2_FB7 CAN_F9R2_FB7_MskFSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)CAN_F2R2_FB25_Pos (25U)LL_DMA_SetPeriphSizeTIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)__GNUCLIKE___SECTION 1SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)GPIO_MODER_MODE12_1 0x02000000UGPIO_IDR_IDR_1 GPIO_IDR_ID1ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)FSMC_SR4_FEMPT_Pos (6U)DMA_HIFCR_CHTIF6_Pos (20U)DMA_LISR_HTIF0_Pos (4U)I2C_CR2_LAST I2C_CR2_LAST_MskSCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)_GLIBCXX_HAVE_GETS 1CAN_F7R1_FB14 CAN_F7R1_FB14_MskINCLUDE_xTaskGetCurrentTaskHandle 0_GLIBCXX_VERBOSE 1CAN_F1R1_FB19 CAN_F1R1_FB19_MskCAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)mt_reqRCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_MskDMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_MskLL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8ENFSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)_GLIBCXX_USE_WEAK_REF __GXX_WEAK__CAN_F10R2_FB6_Pos (6U)RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_MskCAN_F2R2_FB19_Pos (19U)SDIO_MASK_RXDAVLIE_Pos (21U)ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)NVIC_SetPendingIRQ __NVIC_SetPendingIRQpdFAIL ( pdFALSE )TIM6 ((TIM_TypeDef *) TIM6_BASE)CAN_F7R1_FB13_Pos (13U)CAN_F5R1_FB20_Pos (20U)TIM_BDTR_OSSI_Pos (10U)RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)USB_OTG_HCINT_NYET_Pos (6U)USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)GPIO_ODR_OD4 0x00000010UCAN_FFA1R_FFA25 CAN_FFA1R_FFA25_MskDMA_SxFCR_FS DMA_SxFCR_FS_MskETH_DMABMR_RDP_4xPBL_16Beat 0x01080000URCC_CSR_WDGRSTF RCC_CSR_IWDGRSTFRCC_BASE (AHB1PERIPH_BASE + 0x3800UL)CAN_F13R2_FB19 CAN_F13R2_FB19_MskUSART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)CAN_F4R2_FB5 CAN_F4R2_FB5_MskLL_DMA_PERIPH_INCREMENT DMA_SxCR_PINCpdFREERTOS_ERRNO_EBADF 9FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)_CLOCK_T_ unsigned longCAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)ETH_MACSR_MMCS_Pos (4U)taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()configMESSAGE_BUFFER_LENGTH_TYPE size_t__lock_acquire_recursive(lock) __retarget_lock_acquire_recursive(lock)CAN_F9R2_FB9_Pos (9U)SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)pdBIG_ENDIAN pdFREERTOS_BIG_ENDIANUSB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)CAN_F4R2_FB29_Pos (29U)__SIZEOF_WCHAR_T__ 4LL_TIM_COUNTERDIRECTION_UP 0x00000000UDMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)CAN_F7R1_FB30_Pos (30U)RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)TIM_SR_BIF_Pos (7U)USB_OTG_CID_PRODUCT_ID_Pos (0U)CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8))ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)USB_OTG_DOEPINT_STPKTRX_Pos (15U)CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)_GLIBCXX_NAMESPACE_CXX11 __cxx11::xCoRoutineHandle CoRoutineHandle_tCAN_F7R2_FB2 CAN_F7R2_FB2_MskCAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6))SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_MskLL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1ENUSB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_MskCAN_F2R2_FB24 CAN_F2R2_FB24_MskCAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)NVIC_GetEnableIRQ __NVIC_GetEnableIRQTPI_FIFO1_ITM0_Pos 0UCAN_F12R1_FB20_Pos (20U)configPRECONDITION(X) configASSERT( X )___int8_t_defined 1RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)CAN_F9R1_FB17_Pos (17U)ETH_DMABMR_RDP_Pos (17U)DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)CAN_F9R2_FB30_Pos (30U)__FLT32X_HAS_INFINITY__ 1CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)CAN_FA1R_FACT24 CAN_FA1R_FACT24_MskUSB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_MskTIM_DIER_CC3DE TIM_DIER_CC3DE_MskETH_PTPTSSR_TSSPTPOEFE_Pos (11U)EXTI_RTSR_TR1_Pos (1U)EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)CAN_F5R1_FB9 CAN_F5R1_FB9_Msk__FLT32_HAS_INFINITY__ 1CAN_F2R2_FB3_Pos (3U)TIM_SR_CC1IF_Pos (1U)CAN_F4R2_FB9 CAN_F4R2_FB9_MskCAN_F12R1_FB10_Pos (10U)FSMC_PCR4_TCLR FSMC_PCR4_TCLR_MskUSART_CR1_UE USART_CR1_UE_Msk__null_sentinel __attribute__((__sentinel__))CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)CAN_F11R1_FB7 CAN_F11R1_FB7_MskRCC_CR_HSICAL RCC_CR_HSICAL_MskGPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1__cpp_digit_separators 201309LGPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0FLASH_OPTCR_nWRP_5 (0x020UL << FLASH_OPTCR_nWRP_Pos)LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK)CAN_F8R1_FB0 CAN_F8R1_FB0_MskSCB_CCR_STKALIGN_Pos 9ULL_TIM_SR_CC2OF TIM_SR_CC2OFCAN_RF0R_FULL0 CAN_RF0R_FULL0_MskCAN_F7R2_FB0 CAN_F7R2_FB0_MskCAN_F4R1_FB29_Pos (29U)SHIFT_TAB_OISxUSB_OTG_DIEPINT_XFRC_Pos (0U)UINT_LEAST64_MAX __UINT_LEAST64_MAX__CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)TPI_FIFO1_ITM1_Pos 8ULL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOENCAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)RTC_CR_ADD1H RTC_CR_ADD1H_MskADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)LL_GPIO_AF_14 (0x000000EU)ADC_SQR3_SQ4 ADC_SQR3_SQ4_MskFSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)GPIO_AFRH_AFSEL13_3 0x00800000UADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)__FLT_MAX__ 3.4028234663852886e+38FCAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_MskUSB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)EXTI_PR_PR9_Pos (9U)GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2EXTI_IMR_MR13_Pos (13U)USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_MskRCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)CAN_F6R2_FB2 CAN_F6R2_FB2_MskSDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)__returns_twice __attribute__((__returns_twice__))ARM_MPU_AP_RO 6UCAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2ADC_SQR3_SQ5_Pos (20U)__FLT_MANT_DIG__ 24DMA_HISR_FEIF7 DMA_HISR_FEIF7_MskSDIO_CMD_CPSMEN_Pos (10U)CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)FSMC_PMEM2_MEMHOLD2_Pos (16U)_BSD_PTRDIFF_T_ CAN_F9R2_FB0_Pos (0U)GPIO_AFRL_AFSEL5_2 0x00400000ULL_TIM_CLOCKDIVISION_DIV1 0x00000000UCAN_F0R1_FB10_Pos (10U)CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)CAN_F10R1_FB7_Pos (7U)CoreDebug_DEMCR_VC_NOCPERR_Pos 5UITM ((ITM_Type *) ITM_BASE )CAN_F10R2_FB9 CAN_F10R2_FB9_MskGPIO_LCKR_LCKK_Pos (16U)GPIO_AFRH_AFSEL13_2 0x00400000UADC_SR_EOC ADC_SR_EOC_MskRCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_MskFSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)I2C_SR1_ARLO I2C_SR1_ARLO_MskETH_DMABMR_PBL_2Beat 0x00000200UgpioDMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)CAN_FM1R_FBM22 CAN_FM1R_FBM22_MskFSMC_BCR3_MBKEN_Pos (0U)SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_MskCAN_F10R1_FB26 CAN_F10R1_FB26_MskCAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)TIM_DIER_CC1DE_Pos (9U)RCC_CIR_HSIRDYF_Pos (2U)ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)CAN_F13R1_FB6_Pos (6U)CAN_RDT0R_TIME CAN_RDT0R_TIME_MskoffsetofDWT_CTRL_EXCEVTENA_Pos 18USYSCFG_EXTICR4_EXTI14_PF 0x00000500USPI_CR1_BIDIMODE_Pos (15U)DCMI_DR_BYTE3_Pos (24U)LL_DMA_STREAM_1 0x00000001UTIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)ADC_SQR1_SQ16_Pos (15U)EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_MskCAN_F1R1_FB26 CAN_F1R1_FB26_MskxSemaphoreTake(xSemaphore,xBlockTime) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)pdFREERTOS_ERRNO_EFAULT 14DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk_GLIBCXX_HAVE_MEMALIGN 1__ELF__ 1__trylocks_exclusive(...) __lock_annotate(exclusive_trylock_function(__VA_ARGS__))RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)CAN_F0R2_FB1_Pos (1U)SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk_GLIBCXX_BEGIN_NAMESPACE_LDBL SYSCFG_EXTICR4_EXTI12_PF 0x00000005UpdFREERTOS_ERRNO_EADDRNOTAVAIL 125USART_GTPR_GT USART_GTPR_GT_MsklistSET_LIST_INTEGRITY_CHECK_2_VALUE(pxList) EXTI_IMR_MR5_Pos (5U)SCnSCB_ACTLR_DISFOLD_Pos 2UDCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)TPI_DEVID_NrTraceInput_Msk (0x1FUL )ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_MskCAN_FS1R_FSC3 CAN_FS1R_FSC3_MskDWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)CAN_F2R1_FB14_Pos (14U)LL_DMA_SetMemorySizeCAN_FM1R_FBM20_Pos (20U)ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)RCC_SSCGR_SSCGEN_Pos (31U)TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)CAN_F3R1_FB2 CAN_F3R1_FB2_MskFSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)CAN_F12R1_FB15 CAN_F12R1_FB15_MskconfigUSE_DAEMON_TASK_STARTUP_HOOK 0CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)CAN_F4R1_FB30_Pos (30U)SDIO_CLKCR_CLKEN_Pos (8U)portSTACK_TYPE uint32_tADC_SMPR1_SMP18_Pos (24U)SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)__cpp_structured_bindings 201606LADC_CR1_JDISCEN ADC_CR1_JDISCEN_MskEXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)CAN_F3R1_FB12 CAN_F3R1_FB12_Msk__ARM_SIZEOF_MINIMAL_ENUM 1SCB_HFSR_VECTTBL_Pos 1UUSB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)CAN_F2R1_FB4_Pos (4U)LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URSconfigPRE_SLEEP_PROCESSING(x) CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)FLASH_SR_PGSERR_Pos (7U)CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)RCC_APB1RSTR_WWDGRST_Pos (11U)GPIO_IDR_ID5 0x00000020UCAN_FFA1R_FFA22_Pos (22U)TIM_BDTR_DTG_Pos (0U)__noinline __attribute__ ((__noinline__))CAN_FA1R_FACT7 CAN_FA1R_FACT7_MskI2C_CR1_ENGC_Pos (6U)CAN_F4R1_FB24_Pos (24U)ETH_MACCR_JD_Pos (22U)__UTA_FBIT__ 64EXTI_EMR_EM12 EXTI_EMR_MR12CAN_F1R2_FB4 CAN_F1R2_FB4_MskLL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WSI2C_SR2_BUSY I2C_SR2_BUSY_MskEXTI_IMR_IM10 EXTI_IMR_MR10EXTI_FTSR_TR6 EXTI_FTSR_TR6_MskDMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)CAN_F11R1_FB10 CAN_F11R1_FB10_MskADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)TIM_CR1_DIR_Pos (4U)__glibcxx_requires_nonempty() ETH_PTPTTHR_TTSH_Pos (0U)DMA_HIFCR_CTCIF4_Pos (5U)LL_GPIO_AF_10 (0x000000AU)_GLIBCXX_HAS_BUILTIN(B) __has_builtin(B)CAN_FFA1R_FFA16_Pos (16U)ETH_MACMIIAR_CR_Div16_Pos (3U)__COPYRIGHT(s) struct __hackTIM_DIER_COMIE_Pos (5U)USB_OTG_HCCHAR_MPSIZ_Pos (0U)RTC_BKP18R_Pos (0U)USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_MskFSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)ETH_MACFCR_RFCE_Pos (2U)CAN_F1R1_FB6 CAN_F1R1_FB6_MskGPIO_IDR_IDR_12 GPIO_IDR_ID12FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)CAN_F0R2_FB6 CAN_F0R2_FB6_MskEXTI_IMR_IM14 EXTI_IMR_MR14FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)GPIO_AFRH_AFSEL12 0x000F0000ULL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)CAN_F3R2_FB10_Pos (10U)traceQUEUE_RECEIVE(pxQueue) xTimeOutType TimeOut_t__GXX_EXPERIMENTAL_CXX0X__ 1SPI_CR2_SSOE_Pos (2U)RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)APSR_Z_Msk (1UL << APSR_Z_Pos)DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_MskCAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)CAN_F6R1_FB9 CAN_F6R1_FB9_MskRCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_MskUSB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk__cpp_lib_exchange_function 201304LSDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_MskCAN_TSR_ALST0 CAN_TSR_ALST0_MskAPSR_Q_Msk (1UL << APSR_Q_Pos)VTORNVIC ((NVIC_Type *) NVIC_BASE )CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)USB_OTG_DOEPCTL_SODDFRM_Pos (29U)__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)__GNUCLIKE_BUILTIN_STDARG 1CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)TIM14 ((TIM_TypeDef *) TIM14_BASE)CAN_F6R1_FB28_Pos (28U)__SFRACT_EPSILON__ 0x1P-7HRLL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)EXTI_PR_PR9 EXTI_PR_PR9_MskCAN_F11R2_FB6_Pos (6U)SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk_GLIBCXX_DEPRECATED_SUGGEST(ALT) __attribute__ ((__deprecated__ ("use '" ALT "' instead")))ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)__UINT_LEAST32_MAX__ 0xffffffffULADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB )CAN_F2R1_FB25 CAN_F2R1_FB25_MskFSMC_SR3_IFEN FSMC_SR3_IFEN_Msk__wchar_t__ DWT_LSUCNT_LSUCNT_Pos 0URTC_TSTR_SU RTC_TSTR_SU_MskLL_APB2_GRP1_ForceResetCAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)WWDG_CR_T_Pos (0U)USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)CAN_F0R2_FB21 CAN_F0R2_FB21_MskDMA_HISR_DMEIF4 DMA_HISR_DMEIF4_MskUSB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_MskCAN_F12R1_FB19_Pos (19U)FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_MskRCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_MskCAN_TDL1R_DATA1 CAN_TDL1R_DATA1_MskRCC_BDCR_RTCEN RCC_BDCR_RTCEN_MskADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)__SQ_IBIT__ 0USB_OTG_HCINT_ACK_Pos (5U)LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)CAN_F5R2_FB14_Pos (14U)USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)SYSCFG_EXTICR3_EXTI9_PG 0x00000060U_POINTER_INT longFLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)__SIG_ATOMIC_MAX__ 0x7fffffffI2C_CR2_ITERREN I2C_CR2_ITERREN_MskCAN_F4R2_FB18_Pos (18U)USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_MskLL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOPTIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)CAN_F7R2_FB30_Pos (30U)FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_MskRTC_BKP4R_Pos (0U)ETH_MACCR_WD_Pos (23U)DMA_LISR_TEIF2 DMA_LISR_TEIF2_MskCAN_F4R1_FB11 CAN_F4R1_FB11_MskI2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)CAN_F11R1_FB31_Pos (31U)portSTACK_GROWTH ( -1 )CAN_FFA1R_FFA15_Pos (15U)ITM_TCR_ITMENA_Msk (1UL )I2C_CR2_ITEVTEN_Pos (9U)RCC_CIR_HSERDYIE_Pos (11U)CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)CAN_F0R2_FB4_Pos (4U)ARM_MPU_ACCESS_(TypeExtField,IsShareable,IsCacheable,IsBufferable) ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))SCB_CPUID_REVISION_Msk (0xFUL )USART_CR1_M_Pos (12U)RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Mskget_debug_servicer_did_pingCAN_F10R1_FB8 CAN_F10R1_FB8_Msk_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)CAN_F2R2_FB4 CAN_F2R2_FB4_MskDBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_MskCAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)__LARGEFILE_VISIBLE 0__FLT64_DECIMAL_DIG__ 17CAN_F7R2_FB24_Pos (24U)_Thread_local __threadRCC_CFGR_SWS_HSI 0x00000000USPI_I2SCFGR_I2SMOD_Pos (11U)RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)CAN_F13R1_FB18_Pos (18U)CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)CAN_F11R1_FB25_Pos (25U)__FLT_DIG__ 6CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)CAN_F3R2_FB30 CAN_F3R2_FB30_MskFSMC_PMEM3_MEMHIZ3_Pos (24U)TIM_CCMR1_IC1F_Pos (4U)SIGN_GPIO_PERIPH LL_AHB1_GRP1_PERIPH_GPIODSPI_CR2_FRF_Pos (4U)_GLIBCXX_STDC_HEADERS 1LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGENUSB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1CAN_IER_FMPIE0 CAN_IER_FMPIE0_MskI2C_SR1_ADD10 I2C_SR1_ADD10_MskTIM_CCER_CC1NP_Pos (3U)GPIO_MODER_MODE7_1 0x00008000UCAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)operator=CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_MskEXTI_EMR_EM4 EXTI_EMR_MR4ETH_DMAMFBOCR_OFOC_Pos (28U)FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)CAN_F8R2_FB17 CAN_F8R2_FB17_MskCoreDebug_DHCSR_C_DEBUGEN_Pos 0UCAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)configASSERT_DEFINED 1USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)FSMC_PATT2_ATTHOLD2_Pos (16U)LL_GPIO_AF_11 (0x000000BU)RTC_TSTR_ST_Pos (4U)FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR( x )SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)configUSE_MALLOC_FAILED_HOOK 0xPSR_Z_Msk (1UL << xPSR_Z_Pos)PWR_CSR_WUF_Pos (0U)CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_MskGPIO_IDR_ID0 0x00000001UCAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)DMA_LISR_HTIF2_Pos (20U)USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)APSR_V_Pos 28UGPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0CAN_F10R2_FB11_Pos (11U)_MB_LEN_MAX 8RCC_CFGR_PPRE1_Pos (10U)RTC_CR_REFCKON RTC_CR_REFCKON_Msk_SYS_SIZE_T_H _GLIBCXX_RANGES_BASE_H 1CAN_F7R2_FB1_Pos (1U)FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)portTASK_FUNCTION(vFunction,pvParameters) void vFunction( void * pvParameters )CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)__align_down(x,y) __builtin_align_down(x, y)FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)DBGMCU_CR_DBG_STOP_Pos (1U)ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)SYSCFG_EXTICR1_EXTI1_PB 0x00000010UFSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_MskCAN_F9R2_FB28_Pos (28U)I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_MskRCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_MskUSB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)GPIO_BSRR_BS_7 GPIO_BSRR_BS7SDIO_DLEN_DATALENGTH_Pos (0U)CAN_F1R1_FB18_Pos (18U)CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_MskETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)CAN_F11R1_FB21_Pos (21U)FSMC_PATT3_ATTHOLD3_Pos (16U)SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)_PSTL_HIDE_FROM_ABI_PUSH WWDG_CFR_W WWDG_CFR_W_MskCAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk__FRACT_MIN__ (-0.5R-0.5R)traceTASK_CREATE_FAILED() USB_OTG_DOEPMSK_BERRM_Pos (12U)DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_MskDCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)CAN_F11R1_FB7_Pos (7U)CRC_DR_DR CRC_DR_DR_MskFSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)INT_FAST16_MIN_Null_unspecified configUSE_16_BIT_TICKS 0USB_OTG_PCGCCTL_BASE 0xE00ULFSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_MskCAN_F8R2_FB12 CAN_F8R2_FB12_MskCAN_F3R2_FB20_Pos (20U)FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)FSMC_BCR4_MBKEN_Pos (0U)DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)CAN_F11R2_FB2_Pos (2U)CAN_F3R1_FB28_Pos (28U)CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)CAN_TI0R_STID CAN_TI0R_STID_MskTIM_DMAR_DMAB_Pos (0U)USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_MskUSB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_MskFSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_MskEXTI_FTSR_TR7_Pos (7U)USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)SPI_CR1_DFF SPI_CR1_DFF_MskUSB_OTG_FS_MAX_IN_ENDPOINTS 4UADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)WWDG_CFR_W_Pos (0U)CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)EXTI_EMR_MR15 EXTI_EMR_MR15_MskETH_MACFCR_UPFD_Pos (3U)SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_MskCMPCRRCC_APB1LPENR_TIM7LPEN_Pos (5U)MPU_RBAR_REGION_Pos 0U__INTMAX_C(c) c ## LLETH_PTPTSSR_TSSARFE_Pos (8U)ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)ETH_MACA3HR_AE_Pos (31U)CAN_F6R1_FB7 CAN_F6R1_FB7_MskRCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)CAN_F0R1_FB5_Pos (5U)TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)I2C_OAR1_ADD0 I2C_OAR1_ADD0_MskconfigAPPLICATION_ALLOCATED_HEAP 0__CM_CMSIS_VERSION_MAIN ( 5U)CAN_F2R2_FB14_Pos (14U)CAN_F6R2_FB5_Pos (5U)INT16_C(c) __INT16_C(c)DCMI_IER_OVF_IE DCMI_IER_OVR_IERCC_AHB1LPENR_FLITFLPEN_Pos (15U)RTC_WPR_KEY_Pos (0U)CAN_FFA1R_FFA8_Pos (8U)DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_MskCAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)__UINTPTR_TYPE__ unsigned intFSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)CAN_FM1R_FBM26 CAN_FM1R_FBM26_MskRCC_APB1LPENR_TIM14LPEN_Pos (8U)DEPRECATED_DEFINITIONS_H FSMC_BCR2_FACCEN_Pos (6U)SDIO_ICR_RXOVERRC_Pos (5U)FSMC_BCR3_EXTMOD_Pos (14U)pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIANLL_GPIO_AF_9 (0x0000009U)LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2ENETH_MACA2HR_AE_Pos (31U)_GLIBCXX_HAVE_LDEXPF 1I2C_OAR1_ADD1_Pos (1U)FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)EXTI_EMR_MR11_Pos (11U)_GLIBCXX_USE_C99_STDIO _GLIBCXX11_USE_C99_STDIOLL_TIM_LOCKLEVEL_OFF 0x00000000USYSCFG_EXTICR3_EXTI10_PI 0x00000800UCAN_BTR_TS2_Pos (20U)USART_SR_TXE USART_SR_TXE_MskCAN_FA1R_FACT1_Pos (1U)DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_MskFSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_MskDMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)CAN_F4R2_FB24_Pos (24U)DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)CAN_F2R2_FB31_Pos (31U)ETH_DMASR_AIS ETH_DMASR_AIS_Msk_GLIBCXX_USE_DEPRECATED 1ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)SPI_I2SCFGR_I2SE_Pos (10U)RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)PTRDIFF_MIN (-PTRDIFF_MAX - 1)CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)CAN_FA1R_FACT20_Pos (20U)__INT_FAST64_WIDTH__ 64TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_MskAHB1ENR__ARM_ASM_SYNTAX_UNIFIED__ 1TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)__UINT_FAST32_TYPE__ unsigned intDAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_MskconfigMAX_CO_ROUTINE_PRIORITIES (2)FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk_ITERATOR_CONCEPTS_H 1_GLIBCXX_END_INLINE_ABI_NAMESPACE(X) }__cpp_inheriting_constructors 201511LLL_DMA_DisableStreamEXTI_PR_PR0 EXTI_PR_PR0_MskLL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)_GLIBCXX_UTILITY 1DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NEADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_MskCAN_FM1R_FBM14 CAN_FM1R_FBM14_MskCAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)CAN_FS1R_FSC3_Pos (3U)ETH_MACCR_IFG_96Bit 0x00000000UUSB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)CAN_F10R1_FB18 CAN_F10R1_FB18_MskUSART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)traceTASK_SWITCHED_IN() USB_OTG_HCINT_CHH_Pos (1U)DCMI_RIS_OVR_RIS_Pos (1U)__nosanitizeaddress NVIC_GetPendingIRQ __NVIC_GetPendingIRQUSB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)__GNUC_PATCHLEVEL__ 1alloca(size) __builtin_alloca(size)CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_MskCAN_F7R2_FB27_Pos (27U)ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_MskTIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)__USQ_FBIT__ 32CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)__TA_FBIT__ 63RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)TIM_EGR_CC1G TIM_EGR_CC1G_MskCAN_IER_FOVIE0_Pos (3U)USB_OTG_DCTL_TCTL_Pos (4U)INT_LEAST64_MIN (-INT_LEAST64_MAX - 1)CAN_F3R2_FB16 CAN_F3R2_FB16_MskCAN_F9R1_FB9 CAN_F9R1_FB9_MskETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)__INT32_TYPE__ long intCAN_F8R2_FB9 CAN_F8R2_FB9_MskRCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_MskSDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_MskEXTI_IMR_IM6 EXTI_IMR_MR6I2C_OAR1_ADD7_Pos (7U)RTC_CR_POL_Pos (20U)_GLIBCXX_USE_CXX11_ABI 1CAN_F10R2_FB25 CAN_F10R2_FB25_MskCAN_F6R2_FB28_Pos (28U)USB_OTG_DCFG_NZLSOHSK_Pos (2U)RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)USB_OTG_PKTSTS_Pos (17U)dbgtimCAN_F10R1_FB29_Pos (29U)EXTI_FTSR_TR10 EXTI_FTSR_TR10_MskGPIO_BSRR_BR_14 GPIO_BSRR_BR14RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_MsktraceEVENT_GROUP_CREATE(xEventGroup) ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msktask_stackIWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)CAN_F13R2_FB22_Pos (22U)PWR_CR_PLS_LEV4 0x00000080UGPIO_ODR_ODR_1 GPIO_ODR_OD1USART_SR_NE USART_SR_NE_MskCAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)FLASH_ACR_PRFTEN_Pos (8U)SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)CAN_F3R1_FB9_Pos (9U)CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)__FLT64_DIG__ 15EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)CAN_MSR_RXM_Pos (9U)LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_MskCAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)__LFRACT_FBIT__ 31LL_TIM_SR_CC2IF TIM_SR_CC2IFSysTick_LOAD_RELOAD_Pos 0UUINT32_CCAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)RTC_BKP12R RTC_BKP12R_MskCAN_F3R1_FB31 CAN_F3R1_FB31_MskCAN_F9R1_FB23_Pos (23U)FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)RCC_APB1LPENR_TIM3LPEN_Pos (1U)xSemaphoreHandle SemaphoreHandle_tCAN_F6R2_FB10 CAN_F6R2_FB10_MskCoreDebug_DHCSR_C_MASKINTS_Pos 3URCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)ADC_CR2_ALIGN ADC_CR2_ALIGN_MskRTC_BASE (APB1PERIPH_BASE + 0x2800UL)DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_MskEXTI_FTSR_TR1_Pos (1U)FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)ETH_DMABMR_RTPR ETH_DMABMR_RTPR_MskCAN_F12R2_FB14 CAN_F12R2_FB14_Msk__HQ_FBIT__ 15xSemaphoreCreateMutexStatic(pxMutexBuffer) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )_GLIBCXX17_INLINE inlineCAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)DAC_DHR8RD_DACC1DHR_Pos (0U)USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)_GLIBCXX11_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)__cpp_nsdmi 200809LLL_GPIO_WriteReg(__INSTANCE__,__REG__,__VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))CAN_F3R1_FB27 CAN_F3R1_FB27_MskRTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)__USACCUM_IBIT__ 8USART_CR1_RWU USART_CR1_RWU_MskUSART_SR_NE_Pos (2U)TypeRefreshGrabberRCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_MskRCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_MskUSB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_MskCAN_F6R1_FB27 CAN_F6R1_FB27_MskLL_TIM_BREAK_POLARITY_LOW 0x00000000UtskKERNEL_VERSION_BUILD 0CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)FLASHSIZE_BASE 0x1FFF7A22ULCAN_FMR_CAN2SB CAN_FMR_CAN2SB_MskDCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk__INT64_MAX__ 0x7fffffffffffffffLLCAN_F13R2_FB0 CAN_F13R2_FB0_MskEXTI_EMR_MR22 EXTI_EMR_MR22_MskUSB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_MskCAN_F10R1_FB14_Pos (14U)RTC_ALRMAR_DT RTC_ALRMAR_DT_MskCAN_F11R2_FB25_Pos (25U)RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)CAN_F2R2_FB29 CAN_F2R2_FB29_Msk11TIM_TypeDefEXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)_REENT_CHECK_MP(ptr) UINT16_C(c) __UINT16_C(c)DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)UART5_IRQn__thumb2__ 1FLASH_OPTCR_nRST_STDBY_Pos (7U)DAC_CR_MAMP1_Pos (8U)USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_MskCAN_F10R2_FB31_Pos (31U)FSMC_BCR3_BURSTEN_Pos (8U)_LONG_DOUBLE long doubleCAN_F5R2_FB2_Pos (2U)USB_OTG_DIEPMSK_INEPNMM_Pos (5U)__cpp_lib_int_pow2 202002LEXTI_EMR_MR4_Pos (4U)__UINT_FAST8_MAX__ 0xffffffffUCAN_TSR_ALST1_Pos (10U)RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)CAN_TDT2R_TIME_Pos (16U)TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)CAN_F8R1_FB13 CAN_F8R1_FB13_MskUSB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)CAN_F2R1_FB18 CAN_F2R1_FB18_MskRCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_MskUSB_OTG_DIEPINT_ITTXFE_Pos (4U)CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)ETH_DMASR_RPS_Fetching_Pos (17U)CAN_F7R1_FB2 CAN_F7R1_FB2_MskDCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)M1ARCAN_TSR_TXOK0_Pos (1U)configUSE_TIME_SLICING 1FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)CAN_F10R1_FB31 CAN_F10R1_FB31_MskNVIC_EncodePriorityCAN_F13R1_FB25 CAN_F13R1_FB25_MskFSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_MskETH_MACFCR_RFCE ETH_MACFCR_RFCE_MskCAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)EXTI_RTSR_TR21_Pos (21U)__FLT_MAX_10_EXP__ 38EXTI_PR_PR13_Pos (13U)CAN_F13R2_FB29_Pos (29U)TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)RCC_CSR_LSIRDY RCC_CSR_LSIRDY_MskRCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)__cpp_lib_void_t 201411LCAN_F4R2_FB14_Pos (14U)EXTI_FTSR_TR18_Pos (18U)EXTI_EMR_MR7_Pos (7U)CAN_F6R1_FB4 CAN_F6R1_FB4_MskRTC_TR_SU_Pos (0U)IWDG_KR_KEY_Pos (0U)CAN_F5R2_FB4 CAN_F5R2_FB4_MskRCC_CFGR_MCO2_Pos (30U)USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)LL_DMA_STREAM_7 0x00000007UIS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)TIM_CR2_CCUS TIM_CR2_CCUS_MskSPI_CR1_RXONLY_Pos (10U)ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)LL_DMA_STREAM_4 0x00000004UUSB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)CAN_FFA1R_FFA11_Pos (11U)ETH_MACFFR_RA_Pos (31U)USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)EspUpdatingETH_MACA2HR_MACA2H_Pos (0U)USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3CAN_F4R1_FB13_Pos (13U)_GLIBCXX_BEGIN_NAMESPACE_ALGO CAN_F8R2_FB29_Pos (29U)CAN_F12R1_FB20 CAN_F12R1_FB20_MskRCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_MskWRITE_REG(REG,VAL) ((REG) = (VAL))FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_MskDT_DELAY_4 ((uint8_t)0x1F)SYSCFG_EXTICR4_EXTI15_Pos (12U)FSMC_BCR3_MUXEN_Pos (1U)USB_OTG_DIEPMSK_XFRCM_Pos (0U)RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)xQueueSetHandle QueueSetHandle_tGPIO_PUPDR_PUPD2_0 0x00000010UTPI_ITATBCTR2_ATREADY1_Msk (0x1UL )CAN_F3R2_FB23 CAN_F3R2_FB23_MskCAN_TDL0R_DATA1 CAN_TDL0R_DATA1_MskRCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)CAN_F4R2_FB6 CAN_F4R2_FB6_MskLL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOPTIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_MskGPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)NULL __null~RCC_APB2RSTR_TIM10RST_Pos (17U)FSMC_BTR3_ADDSET_Pos (0U)FSMC_SR4_IFS_Pos (2U)CAN_FM1R_FBM1 CAN_FM1R_FBM1_MskFSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)CAN_F7R1_FB26 CAN_F7R1_FB26_Mskactive_isrADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)CAN_TDH1R_DATA5_Pos (8U)CAN_F6R1_FB23_Pos (23U)MSN_COLOR_H FSMC_BCR4_WAITEN_Pos (13U)RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)CAN_F1R1_FB26_Pos (26U)SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)I2C_SR1_ADDR I2C_SR1_ADDR_MskTIM_CCER_CC1P_Pos (1U)__UINT16_C(c) cADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)ADC_SQR3_SQ1 ADC_SQR3_SQ1_MskADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)CAN_FS1R_FSC8 CAN_FS1R_FSC8_MskEXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)RCC_APB1LPENR_I2C3LPEN_Pos (23U)FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)FSMC_SR3_IFEN_Pos (5U)LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKPGPIO_MODER_MODE4_1 0x00000200UCAN_F6R1_FB17_Pos (17U)RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_MskADC_CSR_OVR3_Pos (21U)RTC_BKP0R_Pos (0U)USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_MskTIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_MskFSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)USB_OTG_HCCHAR_EPNUM_Pos (11U)listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)IWDG_PR_PR IWDG_PR_PR_MskTIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_MskGPIO_OSPEEDR_OSPEED0_0 0x00000001UETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)DWT_CTRL_SYNCTAP_Pos 10ULL_GPIO_MODE_ANALOG GPIO_MODER_MODER0GPIO_LCKR_LCK1_Pos (1U)CAN_F9R1_FB12 CAN_F9R1_FB12_MskGPIO_AFRL_AFSEL2_0 0x00000100UCAN_F3R1_FB17 CAN_F3R1_FB17_MskEXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)RCC_CFGR_SWS_PLL 0x00000008UEXTI_IMR_MR17 EXTI_IMR_MR17_Msk_GLIBCXX_USE_C99_MATH_TR1 1GPIO_AFRL_AFSEL0_2 0x00000004UCAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)CAN_F1R2_FB24_Pos (24U)USB_OTG_DOEPINT_OTEPDIS_Pos (4U)TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)FLASH_SR_PGSERR FLASH_SR_PGSERR_MskDMA_LISR_FEIF0_Pos (0U)TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_MskUSB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_MskETH_MACSR_PMTS_Pos (3U)CAN_F8R1_FB27_Pos (27U)GPIO_PUPDR_PUPD0 0x00000003UCAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)_ZN5crash20MatrixBitLookupTableILj1EEC4EvFSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)configENABLE_TRUSTZONE 1CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)ETH_MACFFR_SAIF_Pos (8U)CAN_F8R2_FB31 CAN_F8R2_FB31_MskCAN_F8R1_FB2_Pos (2U)GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)__UINT16_TYPE__ short unsigned int_GLIBCXX_HOSTED __STDC_HOSTED__TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)GPIO_AFRL_AFSEL7_1 0x20000000URCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)configUSE_TASK_FPU_SUPPORT 1_GLIBCXX_USE_DUAL_ABI 1GPIO_AFRH_AFSEL15_1 0x20000000USCB_SHCSR_PENDSVACT_Pos 10UUSB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)SDIO_MASK_RXFIFOFIE_Pos (17U)GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)CAN_BTR_TS1 CAN_BTR_TS1_MskSPI_SR_RXNE SPI_SR_RXNE_MskCAN_F0R1_FB8 CAN_F0R1_FB8_MskEXTI_SWIER_SWIER17_Pos (17U)SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0pdFREERTOS_LITTLE_ENDIAN 0USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)DWT_CTRL_PCSAMPLENA_Pos 12UDAC_CR_TEN2 DAC_CR_TEN2_MskCAN_F9R1_FB12_Pos (12U)I2C_SR1_SB I2C_SR1_SB_MskRCC_APB1RSTR_TIM7RST_Pos (5U)EXTI_RTSR_TR10 EXTI_RTSR_TR10_MskCAN_F7R2_FB13_Pos (13U)RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_MskARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)_TIME_T_ __int_least64_tEXTI ((EXTI_TypeDef *) EXTI_BASE)CAN_F11R1_FB14_Pos (14U)__CMSIS_VERSION_H CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)SCB_CCR_USERSETMPEND_Pos 1UCAN_F4R2_FB22 CAN_F4R2_FB22_MskUINT8_MAXFSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2SYSCFG_EXTICR2_EXTI5_PI 0x00000080UFSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)MPU_RBAR_REGION_Msk (0xFUL )RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)CAN_F13R1_FB30_Pos (30U)IWDG_SR_RVU IWDG_SR_RVU_Msk_PSTL_ASSERT(_Condition) __glibcxx_assert(_Condition)USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)TIM_BDTR_BKE_Pos (12U)__SQ_FBIT__ 31ETH_MACCR_TE ETH_MACCR_TE_MskADC_SMPR1_SMP13_Pos (9U)CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_MskRCC_AHB1ENR_ETHMACPTPEN_Pos (28U)CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)__ARM_FEATURE_CDE_COPROCSCB_SHCSR_SVCALLPENDED_Pos 15UCAN_FFA1R_FFA0 CAN_FFA1R_FFA0_MskETH_DMASR_RWTS_Pos (9U)CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)CAN_F9R2_FB23_Pos (23U)LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11ENGPIO_AFRL_AFSEL5_3 0x00800000UCAN_F6R1_FB3 CAN_F6R1_FB3_MskADC_CSR_JEOC1_Pos (2U)GPIO_OSPEEDR_OSPEED5_0 0x00000400U__ARM_FP16_ARGSCAN_F13R1_FB24_Pos (24U)CAN_F1R2_FB1 CAN_F1R2_FB1_MskDBGMCU_CR_TRACE_IOEN_Pos (5U)RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)__ULFRACT_MIN__ 0.0ULR_PSTL_MONOTONIC_PRESENT (__INTEL_COMPILER >= 1800)TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)GPIO_MODER_MODER12 GPIO_MODER_MODER12_MskCAN_F7R2_FB18 CAN_F7R2_FB18_MskRTC_CR_FMT RTC_CR_FMT_MskRTC_DR_MU_Pos (8U)SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk__PTRDIFF_WIDTH__ 32CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)CAN_F0R2_FB13 CAN_F0R2_FB13_MskDMA_SxCR_CHSEL_Pos (25U)ADC_JDR4_JDATA ADC_JDR4_JDATA_MskRCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_MskSCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)__ARM_FEATURE_LDREXDMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)__cpp_consteval 201811LCAN_TDL1R_DATA2_Pos (16U)_RANGES_CMP_H 1RCC_AHB1RSTR_GPIOHRST_Pos (7U)USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)ETH_DMAOMR_TSF ETH_DMAOMR_TSF_MskDAC_CR_TSEL1_Pos (3U)TIM_CCMR2_OC3M_Pos (4U)I2C2_EV_IRQnGPIO_PUPDR_PUPD15 0xC0000000UGPIO_AFRL_AFSEL5_0 0x00100000UFSMC_PCR3_TCLR_Pos (9U)CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)CAN_F1R1_FB30_Pos (30U)SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)traceSTREAM_BUFFER_RECEIVE(xStreamBuffer,xReceivedLength) DT_DELAY_2 ((uint8_t)0x3F)SPI1_IRQnGPIO_AFRH_AFSEL13_0 0x00100000UCAN_F12R2_FB10_Pos (10U)PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)TIM_CCER_CC2P_Pos (5U)GPIO_BSRR_BR_13 GPIO_BSRR_BR13TypeRxTimeCAN_F13R2_FB16 CAN_F13R2_FB16_MskCAN_F0R1_FB18_Pos (18U)ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_MskGPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)APB1RSTRFSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)TIM2_IRQnDMA_HIFCR_CDMEIF7_Pos (24U)RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_MskCAN_FMR_FINIT_Pos (0U)CAN_F9R2_FB30 CAN_F9R2_FB30_MskCAN_F3R1_FB17_Pos (17U)LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU_GLIBCXX_HAVE_BUILTIN_IS_AGGREGATE 1USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)CAN_F6R2_FB2_Pos (2U)TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_MskUSB_OTG_DCFG_PFIVL_Pos (11U)RTC_CALIBR_DCS RTC_CALIBR_DCS_MskETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)__UDA_FBIT__ 32FSMC_PMEM2_MEMHIZ2_Pos (24U)DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_MskUSB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)SPI_I2SPR_I2SDIV_Pos (0U)__USES_INITFINI__ 1CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)NVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingAHB2RSTRETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_MskTPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)CAN_RDT0R_TIME_Pos (16U)ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_MskETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)I2C_SR1_SB_Pos (0U)RNG_IRQnFSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk~CalibrationRequestCAN_RF0R_RFOM0_Pos (5U)CAN_IER_EPVIE CAN_IER_EPVIE_MskGPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_MskDMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)CAN_F3R1_FB24 CAN_F3R1_FB24_Msk19LL_GPIO_InitTypeDef__need_size_tCAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)FSMC_SR4_FEMPT FSMC_SR4_FEMPT_MskTIM_DIER_BIE TIM_DIER_BIE_MskARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)CAN_F0R2_FB10_Pos (10U)bt_lenFLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)EXTI_IMR_MR19 EXTI_IMR_MR19_MskFSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)SDIO_STA_RXFIFOE_Pos (19U)USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)___int_least16_t_defined 1ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_MskIWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)CAN_TDT0R_DLC CAN_TDT0R_DLC_MskDMA_LIFCR_CHTIF2_Pos (20U)TIM_CR2_OIS1_Pos (8U)USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_MskCAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)IS_TIM_CCX_INSTANCE(INSTANCE,CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM5) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM8) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) || (((INSTANCE) == TIM9) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM10) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM11) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM12) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))) || (((INSTANCE) == TIM13) && (((CHANNEL) == TIM_CHANNEL_1))) || (((INSTANCE) == TIM14) && (((CHANNEL) == TIM_CHANNEL_1))))USART3_BASE (APB1PERIPH_BASE + 0x4800UL)USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)FLASH_OPTCR_nWRP_0 (0x001UL << FLASH_OPTCR_nWRP_Pos)CAN_FM1R_FBM17_Pos (17U)ETH_DMABMR_RDP_32Beat 0x00400000UTPI_FIFO1_ITM_ATVALID_Pos 29UGPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)_ZN5crash10print_lineEPKchtbLL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1RTC_ALRMBR_DU RTC_ALRMBR_DU_MskSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )NVIC_SRV_TX_ACTV LL_DMA_IsActiveFlag_TC7RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_MskCAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)CAN_MSR_ERRI_Pos (2U)SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)FSMC_SR3_IRS_Pos (0U)CAN_F5R1_FB10 CAN_F5R1_FB10_MskFSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)__UINT_LEAST16_TYPE__ short unsigned int_STL_ALGO_H 1CAN_F2R2_FB20_Pos (20U)xPSR_ICI_IT_2_Pos 25URCC_CFGR_HPRE_DIV256 0x000000E0UCAN_F3R1_FB15_Pos (15U)USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)TIM_DIER_CC3DE_Pos (11U)FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)GPIO_LCKR_LCK12_Pos (12U)SDIO_STA_TXUNDERR_Pos (4U)RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)SYSCFG_EXTICR4_EXTI15_PE 0x00004000UFSMC_ECCR3_ECC3_Pos (0U)vQueueAddToRegistry(xQueue,pcName) __LL_TIM_CALC_DEADTIME(__TIMCLK__,__CKD__,__DT__) ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) : (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) : (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) : 0U)SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)CAN_F0R2_FB17_Pos (17U)ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)DMA1_Stream0_IRQnCAN_F11R1_FB28 CAN_F11R1_FB28_Msk_WANT_IO_LONG_LONG 1SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_MskSDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk_GLIBCXX_HAVE_LC_MESSAGES 1CAN_RDH1R_DATA5_Pos (8U)ms_assert msign_assertSDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_MskGPIO_AFRH_AFSEL11 0x0000F000UCAN_F11R2_FB18_Pos (18U)__locks_shared(...) __lock_annotate(shared_lock_function(__VA_ARGS__))_GLIBCXX_INT_N_TRAITSCAN_F4R2_FB10 CAN_F4R2_FB10_MskPWR_CR_PVDE PWR_CR_PVDE_MskRCC_CR_PLLRDY_Pos (25U)CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)SYSCFG_EXTICR4_EXTI15_PB 0x00001000UGPIO_IDR_ID3 0x00000008UUSB_OTG_GINTMSK_WUIM_Pos (31U)DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_MskRTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)CAN_F4R2_FB30_Pos (30U)FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_MskCAN_F10R1_FB24_Pos (24U)USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)RCC_CR_CSSON RCC_CR_CSSON_Msk__LLACCUM_IBIT__ 32ETH_PTPTSHR_STS ETH_PTPTSHR_STS_MskETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_MskRCC_APB1RSTR_PWRRST_Pos (28U)USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)__LLACCUM_EPSILON__ 0x1P-31LLKDCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)USB_OTG_HCINT_BBERR_Pos (8U)CAN_F3R1_FB4_Pos (4U)TPI_ITATBCTR0_ATREADY2_Pos 0UCAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)DCMI_CR_PCKPOL DCMI_CR_PCKPOL_MsktaskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )_GLIBCXX_END_NAMESPACE_LDBL ETH_MACFCR_TFCE ETH_MACFCR_TFCE_MskCAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)USB_OTG_GAHBCFG_DMAEN_Pos (5U)RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)CAN_F10R1_FB23 CAN_F10R1_FB23_MskCAN_F6R2_FB17_Pos (17U)INC_TASK_H USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_MskADC3 ((ADC_TypeDef *) ADC3_BASE)CAN_F13R1_FB17 CAN_F13R1_FB17_MskCAN_F10R1_FB18_Pos (18U)ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk__cpp_unicode_characters 201411LCAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)PWR_CSR_BRE_Pos (9U)CAN_F0R2_FB20 CAN_F0R2_FB20_MskTIM_CCER_CC3P TIM_CCER_CC3P_MskTIM_CR1_CMS TIM_CR1_CMS_MskSCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_MskCAN_F6R1_FB3_Pos (3U)TIM_CCER_CC3P_Pos (9U)DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk_T_SIZE TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)CAN_F0R2_FB23 CAN_F0R2_FB23_MskGPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15__INT16_C(c) cESP_USART_IRQ_NAME USART6_IRQnUSB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_MskCAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)USART_CR3_CTSIE_Pos (10U)RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)UINTMAX_MAX __UINTMAX_MAX__ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)CAN_F10R2_FB30 CAN_F10R2_FB30_MskCAN_F12R1_FB0 CAN_F12R1_FB0_MskDMA_SxFCR_DMDIS_Pos (2U)FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_MskETH_DMAOMR_TSF_Pos (21U)CAN_F8R2_FB27_Pos (27U)RCC_AHB1ENR_GPIOFEN_Pos (5U)CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)EXTI_IMR_IM20 EXTI_IMR_MR20CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)CAN_F12R1_FB28_Pos (28U)RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_MskCAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)CAN_F12R1_FB12 CAN_F12R1_FB12_MskDBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)USB_OTG_HAINTMSK_HAINTM_Pos (0U)DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_MskLL_DMA_CURRENTTARGETMEM0 0x00000000UFSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)ESP_USART_RX LL_GPIO_PIN_9EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Mskdma_bufferPWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)CAN_FS1R_FSC17 CAN_FS1R_FSC17_MskUSART_CR3_IREN USART_CR3_IREN_MskCAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)SDIO_MASK_CMDSENTIE_Pos (7U)LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOPUSB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)SYSCFG_EXTICR3_EXTI11_PE 0x00004000UUSB_OTG_DOEPINT_XFRC_Pos (0U)CAN_F12R2_FB6_Pos (6U)_GLIBCXX_BEGIN_NAMESPACE_CONTAINER CAN_F7R1_FB19 CAN_F7R1_FB19_MskCAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)CAN_FA1R_FACT4 CAN_FA1R_FACT4_MskETH_DMABMR_RTPR_2_1 0x00004000UCAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)CAN_F0R1_FB14 CAN_F0R1_FB14_MskRCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)TPI_ITCTRL_Mode_Msk (0x3UL )RCC_APB2ENR_SDIOEN_Pos (11U)CAN_F11R2_FB14_Pos (14U)EXTI_SWIER_SWIER4_Pos (4U)SysTick ((SysTick_Type *) SysTick_BASE )CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)__INT_WCHAR_T_H TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)CAN_FA1R_FACT14 CAN_FA1R_FACT14_MskFSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_MskUSB_OTG_GINTMSK_GINAKEFFM_Pos (6U)ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)xTimerHandle TimerHandle_tCAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)EXTI_FTSR_TR6_Pos (6U)FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)__GCC_ATOMIC_INT_LOCK_FREE 2__INT8_C(c) c__P(protos) protosADC_SQR3_SQ4_Pos (15U)CONTROL_nPRIV_Msk (1UL )CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)USART1 ((USART_TypeDef *) USART1_BASE)ADC_CSR_AWD3 ADC_CSR_AWD3_MskCAN_F0R1_FB28_Pos (28U)RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)errQUEUE_BLOCKED ( -4 )DBGMCU_IDCODE_DEV_ID_Pos (0U)xQueueSendToFrontFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )CAN_TDH2R_DATA4_Pos (0U)FLASH_ACR_DCRST_Pos (12U)DCMI_ICR_OVR_ISC_Pos (1U)listFIRST_LIST_INTEGRITY_CHECK_VALUE EXTI_RTSR_TR1 EXTI_RTSR_TR1_MskUSB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)CAN_F13R2_FB24_Pos (24U)UINT_LEAST32_MAX __UINT_LEAST32_MAX__ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)CAN_F11R2_FB31_Pos (31U)USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)ADC_CR2_EXTSEL ADC_CR2_EXTSEL_MskI2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk_EXT_TYPE_TRAITS 1AIRCRCAN_F1R2_FB4_Pos (4U)ETH_DMAOMR_ST_Pos (13U)ETH_DMABMR_RTPR_Pos (14U)CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_MskUSART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)GPIO_PUPDR_PUPD6 0x00003000UUSB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOPADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)DAC_DHR12RD_DACC2DHR_Pos (16U)ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)DCMI_CR_CAPTURE DCMI_CR_CAPTURE_MskCAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)USB_OTG_GINTMSK_RXFLVLM_Pos (4U)CAN_F9R2_FB4 CAN_F9R2_FB4_MskETH_DMAIER_RPSIE_Pos (8U)CAN_FA1R_FACT22 CAN_FA1R_FACT22_MskEXTI_RTSR_TR10_Pos (10U)TIM_BDTR_LOCK_Pos (8U)CAN_F13R2_FB18_Pos (18U)CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)ETH_DMAOMR_OSF_Pos (2U)SDIO_STA_RXACT SDIO_STA_RXACT_Msk__HQ_IBIT__ 0CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)_GLIBCXX_USE_C99_INTTYPES_WCHAR_T_TR1 1FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)CAN_F4R2_FB3_Pos (3U)ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_MskCAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_MskUSB_OTG_HCINTMSK_FRMORM_Pos (9U)RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)__glibcxx_requires_can_decrement_range(_First1,_Last1,_First2) _GCC_WCHAR_T DAC_DHR12LD_DACC1DHR_Pos (4U)EXTI4_IRQnCAN_F13R1_FB30 CAN_F13R1_FB30_MskUSB_OTG_GINTMSK_HCIM_Pos (25U)IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCERCC_APB2LPENR_USART1LPEN_Pos (4U)I2C_CR2_LAST_Pos (12U)CAN_F8R2_FB6 CAN_F8R2_FB6_MskFSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)TPI_ITATBCTR0_ATREADY1_Pos 0UADC_CDR_DATA1 ADC_CDR_DATA1_MskGPIO_OSPEEDR_OSPEED0 0x00000003U__UFRACT_EPSILON__ 0x1P-16URGPIO_IDR_IDR_5 GPIO_IDR_ID5GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))uxDummy2uxDummy4uxDummy5WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)STM32F207xx 1RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)USB_OTG_GRSTCTL_AHBIDL_Pos (31U)ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)USB_OTG_DOEPINT_STUP_Pos (3U)DMA_SxCR_DIR DMA_SxCR_DIR_MskCAN_F4R2_FB15 CAN_F4R2_FB15_MskDMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)GPIO_IDR_IDR_2 GPIO_IDR_ID2CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)BDCR__DEC_EVAL_METHOD__ 2__cpp_impl_destroying_delete 201806L_GLIBCXX_HAVE_ATAN2F 1TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)xPSR_Q_Pos 27UTIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)__dead2 __attribute__((__noreturn__))GPIO_OTYPER_OT11 0x00000800UETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)ADC_CR2_SWSTART ADC_CR2_SWSTART_MskTIM_CCMR2_OC3M TIM_CCMR2_OC3M_MskETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk__cpp_lib_constexpr_memory 201811LSDIO_CMD_CMDINDEX_Pos (0U)FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)CAN_F1R2_FB18_Pos (18U)_STL_ALGOBASE_H 1SDIO_CMD_WAITPEND_Pos (9U)CAN_F8R1_FB18 CAN_F8R1_FB18_MskCAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)CAN_F6R1_FB12_Pos (12U)CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)EXTI_FTSR_TR15_Pos (15U)TIM_CCMR1_CC1S_Pos (0U)FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_MskDAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_MskUSB_OTG_GCCFG_NOVBUSSENS_Pos (21U)CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)INT_LEAST8_MAX __INT_LEAST8_MAX__RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)CAN_F11R2_FB19 CAN_F11R2_FB19_MskCAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)EXTI_EMR_MR7 EXTI_EMR_MR7_MskCAN_F12R1_FB7_Pos (7U)__lock_try_acquire_recursive(lock) __retarget_lock_try_acquire_recursive(lock)DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)DMA_SxCR_PL_Pos (16U)__DA_FBIT__ 31FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_MskETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_MskRCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_MskxTaskStatusType TaskStatus_tADC_CR2_EXTEN ADC_CR2_EXTEN_MskCAN_FS1R_FSC23_Pos (23U)CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)_GLIBCXX_USE_C99_WCHAR _GLIBCXX11_USE_C99_WCHARSDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_MskUSB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)ETH_MMCTIMR_TGFSCM_Pos (14U)RCC_CFGR_SW_HSI 0x00000000UFSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)DAC_DHR12R1_DACC1DHR_Pos (0U)__FLT32X_DECIMAL_DIG__ 17CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)CAN_F3R2_FB28_Pos (28U)CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISCCAN_TDL0R_DATA3_Pos (24U)CAN_F8R1_FB22_Pos (22U)MISSING_IGNOREWWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)USE_FULL_LL_DRIVER 1FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)SPI_CR1_CPHA SPI_CR1_CPHA_MskCAN_RI1R_RTR_Pos (1U)_GLIBCXX_INT_N_TRAITS(T,WIDTH) __extension__ template<> struct __is_integer_nonstrict { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = WIDTH }; }; __extension__ template<> struct __is_integer_nonstrict { enum { __value = 1 }; typedef std::__true_type __type; enum { __width = WIDTH }; };CAN_FS1R_FSC17_Pos (17U)__USFRACT_EPSILON__ 0x1P-8UHRCAN_RDL1R_DATA3 CAN_RDL1R_DATA3_MskETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)RCC_CR_HSEBYP RCC_CR_HSEBYP_MskUSB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)GPIO_BSRR_BR_0 GPIO_BSRR_BR0SHIFT_TAB_OCxxtraceTASK_INCREMENT_TICK(xTickCount) CAN_F13R2_FB9 CAN_F13R2_FB9_Msk_GLIBCXX_NAMESPACE_LDBL GPIO_PUPDR_PUPD11_1 0x00800000UCAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)ETH_MACA1HR_MACA1H_Pos (0U)USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)RTC_ALRMAR_PM_Pos (22U)CAN_F8R1_FB16_Pos (16U)GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0GPIO_OSPEEDR_OSPEED9_0 0x00040000UCAN_F0R1_FB21 CAN_F0R1_FB21_MskFLASH_OPTCR_BOR_LEV_1 0x00000008UTIM_CCER_CC3NP TIM_CCER_CC3NP_MskRCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_MskCAN_F1R1_FB5_Pos (5U)CAN_F9R2_FB23 CAN_F9R2_FB23_MskETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_MskCAN_F4R1_FB8 CAN_F4R1_FB8_MskCAN_F3R2_FB28 CAN_F3R2_FB28_MskCAN_F0R1_FB7_Pos (7U)FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)CAN_F3R2_FB8 CAN_F3R2_FB8_Msk_REENT_CHECK_VERIFY 1_GLIBCXX_OS_DEFINES 1RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_MskDMA_SxFCR_FEIE_Pos (7U)CAN_F6R2_FB4_Pos (4U)I2C_SR1_TXE I2C_SR1_TXE_MskTPI_FIFO1_ITM_bytecount_Pos 27UADC_SMPR2_SMP7_Pos (21U)_NULL 0ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)GPIO_PUPDR_PUPD11_0 0x00400000UCAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)RCC_AHB1ENR_GPIOCEN_Pos (2U)INCLUDE_uxTaskGetStackHighWaterMark 0PVD_IRQnGPIO_PUPDR_PUPD4_1 0x00000200UCAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)CAN_F4R1_FB4_Pos (4U)portEXIT_CRITICAL() vPortExitCritical()RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)__DOUBLE_TYPE double__ARM_FEATURE_DOTPROD_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); _REENT_INIT_PTR_ZEROED(var); }USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)NonMaskableInt_IRQn__ULLACCUM_IBIT__ 32CAN_F7R2_FB19_Pos (19U)USB_OTG_GUSBCFG_TOCAL_Pos (0U)DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)CAN_F11R1_FB1 CAN_F11R1_FB1_MskDMA_SxCR_PFCTRL_Pos (5U)LL_TIM_SR_UIF TIM_SR_UIFCAN_TSR_CODE_Pos (24U)pdFREERTOS_ERRNO_EFTYPE 79USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_MskTPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)CRC ((CRC_TypeDef *) CRC_BASE)CAN_F10R2_FB18_Pos (18U)CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)CAN_F5R2_FB14 CAN_F5R2_FB14_MskLL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1CAN_F9R2_FB11 CAN_F9R2_FB11_MskRCC_AHB1LPENR_GPIODLPEN_Pos (3U)CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)RTC_ALRMBR_HT_Pos (20U)FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2ETH_DMABMR_PBL_8Beat 0x00000800UUSB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_MskGPIO_AFRL_AFSEL3_1 0x00002000UFSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)CAN_F5R2_FB1 CAN_F5R2_FB1_MskDMA_SxCR_PSIZE_Pos (11U)USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)GPIO_AFRH_AFSEL11_1 0x00002000UCAN_F8R2_FB24 CAN_F8R2_FB24_MskETH_MMCTIR_TGFSCS_Pos (14U)CAN_F6R2_FB25 CAN_F6R2_FB25_MskCAN_TI1R_RTR CAN_TI1R_RTR_MsktraceFREE(pvAddress,uiSize) GPIO_AFRL_AFSEL3_2 0x00004000UETH ((ETH_TypeDef *) ETH_BASE)TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)TIM_DCR_DBA TIM_DCR_DBA_MskUSB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)GPIO_AFRH_AFSEL11_2 0x00004000UCAN_F9R2_FB12_Pos (12U)LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9ENCAN_F13R1_FB13_Pos (13U)GPIO_PUPDR_PUPD14_1 0x20000000UETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk_READ_WRITE_RETURN_TYPE intCAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)CAN_F10R2_FB7_Pos (7U)__throw_exception_again TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)DMA_LISR_TCIF3 DMA_LISR_TCIF3_MskconfigSUPPORT_STATIC_ALLOCATION 1_WANT_USE_GDTOA 1RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)GPIO_MODER_MODE13_1 0x08000000USCB_SCR_SLEEPDEEP_Pos 2U_GLIBCXX_HAVE_WCSTOF 1GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_MskTIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)UART_UART_PERIPH LL_APB2_GRP1_PERIPH_USART6EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_MskCAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)CAN_RF1R_FOVR1_Pos (4U)USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)CAN_FFA1R_FFA0_Pos (0U)EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_MskDBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_MskCAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)ETH_DMABMR_RDP_16Beat 0x00200000UUSB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U__ATFILE_VISIBLE 1ETH_DMASR_TSTS_Pos (29U)ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)FSMC_BCR3_MWID_Pos (4U)RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)USB_OTG_HCSPLT_HUBADDR_Pos (7U)_GLIBCXX_HAVE_SYS_STAT_H 1USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)RTC_TR_PM_Pos (22U)__cpp_rvalue_reference 200610LCAN_F8R1_FB25 CAN_F8R1_FB25_Msk__FLT32_MAX__ 3.4028234663852886e+38F32DMA_SxCR_HTIE_Pos (3U)CAN_F5R2_FB10 CAN_F5R2_FB10_MskSDIO_CLKCR_HWFC_EN_Pos (14U)CAN_F1R1_FB20 CAN_F1R1_FB20_MskCAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_MskEXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)CAN_F2R1_FB1 CAN_F2R1_FB1_Msk_STDBOOL_H CAN_F1R1_FB13_Pos (13U)CAN_F4R2_FB27 CAN_F4R2_FB27_MskCAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk__ARM_FEATURE_SIMD32CAN_F0R2_FB28_Pos (28U)CAN_F10R1_FB15 CAN_F10R1_FB15_MskDMA_LIFCR_CTEIF0_Pos (3U)TIM5 ((TIM_TypeDef *) TIM5_BASE)ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_MskCAN_F12R2_FB1 CAN_F12R2_FB1_MskETH_DMARPDR_RPD ETH_DMARPDR_RPD_MskRCC_CSR_PINRSTF RCC_CSR_PINRSTF_MskTIMx_GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER(A) CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)TPI_FIFO0_ETM_bytecount_Pos 24UCAN_F13R2_FB21 CAN_F13R2_FB21_MskDMA_LIFCR_CHTIF0_Pos (4U)9IRQn_TypeCAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)EXTI_PR_PR18 EXTI_PR_PR18_MskUSB_OTG_GINTSTS_ISOODRP_Pos (14U)EXTI_RTSR_TR2_Pos (2U)USB_OTG_GOTGCTL_DHNPEN_Pos (11U)ETH_MACFFR_HU ETH_MACFFR_HU_MskDBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Mskget_debug_servicer_pending_requests_PSTL_PRAGMA_LOCATION " [Parallel STL message]: "__STDC_UTF_32__ 1listGET_NEXT(pxListItem) ( ( pxListItem )->pxNext )CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)TPI_FIFO1_ETM_ATVALID_Pos 26UCAN_F0R2_FB3 CAN_F0R2_FB3_MskSPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_MskDWT_FUNCTION_DATAVADDR0_Pos 12ULL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1ENCAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)CAN_F3R1_FB23_Pos (23U)CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)GPIO_MODER_MODE11_0 0x00400000USYSCFG_EXTICR2_EXTI5_PG 0x00000060UCAN_F10R2_FB22 CAN_F10R2_FB22_MskDCMI_DR_BYTE0_Pos (0U)portTICK_RATE_MS portTICK_PERIOD_MSUSB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)CAN_TI0R_EXID_Pos (3U)CAN_TI0R_TXRQ CAN_TI0R_TXRQ_MskSPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)CAN_F0R2_FB18 CAN_F0R2_FB18_Msk_PSTL_PRAGMA_SIMD_EXCLUSIVE_SCAN(PRM) CAN_FA1R_FACT27_Pos (27U)ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_MskWCHAR_MIN __WCHAR_MIN__USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )FLASH_ACR_LATENCY FLASH_ACR_LATENCY_MskRTC_ISR_TSOVF RTC_ISR_TSOVF_MskUSB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_MskUSB_OTG_GUSBCFG_CTXPKT_Pos (31U)_ecdataUSART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_MskCAN_F0R1_FB5 CAN_F0R1_FB5_MskEXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1CAN_BTR_SILM CAN_BTR_SILM_Msk_GLIBCXX_HAVE_ASINF 1USB_OTG_GINTMSK_SOFM_Pos (3U)__UACCUM_MAX__ 0XFFFFFFFFP-16UKRCC_APB1LPENR_USART2LPEN_Pos (17U)USB_OTG_GINTSTS_USBRST_Pos (12U)_ZN5crash4draw4rectERNS_6MatrixEtttthRCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)__cpp_lib_tuples_by_type 201304LFSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)FSMC_BCR3_ASYNCWAIT_Pos (15U)USB_OTG_HCINT_STALL_Pos (3U)SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)DMA_LISR_FEIF3 DMA_LISR_FEIF3_MskFSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)TIM_CR2_CCPC TIM_CR2_CCPC_MskLL_TIM_DIER_TIE TIM_DIER_TIESDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_MskDBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)errQUEUE_EMPTY ( ( BaseType_t ) 0 )_GLIBCXX14_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)CAN_F12R2_FB11 CAN_F12R2_FB11_MskRTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)CAN_RDT1R_TIME CAN_RDT1R_TIME_MskGPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1__UINTPTR_MAX__ 0xffffffffUnvicGPIO_MODER_MODE14_1 0x20000000UDWT_CTRL_EXCTRCENA_Pos 16UCAN_F10R1_FB8_Pos (8U)SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )RCC_APB1RSTR_I2C1RST_Pos (21U)USB_OTG_DCTL_RWUSIG_Pos (0U)CAN_F11R1_FB21 CAN_F11R1_FB21_MskADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)GPIO_BSRR_BR10 0x04000000UServicerFSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)_GLIBCXX_HAVE_CEILF 1CAN_F5R2_FB21 CAN_F5R2_FB21_MskETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_MsktraceTASK_DELETE(pxTaskToDelete) SYSCFG_EXTICR2_EXTI6_PI 0x00000800UDBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)GPIO_OSPEEDR_OSPEED5_1 0x00000800UTIM_EGR_CC3G_Pos (3U)__SSAT(ARG1,ARG2) __extension__ ({ int32_t __RES, __ARG1 = (ARG1); __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); __RES; })USB_OTG_GCCFG_PWRDWN_Pos (16U)FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)ETH_DMABMR_AAB ETH_DMABMR_AAB_MskETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)CAN_F10R1_FB13_Pos (13U)CAN_F10R2_FB13_Pos (13U)SCnSCB_ACTLR_DISDEFWBUF_Pos 1UCAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)ETH_MACSR_MMCTS_Pos (6U)RTC_ALRMBR_MNU RTC_ALRMBR_MNU_MskRCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)CAN_F13R1_FB7_Pos (7U)CAN_F9R1_FB24 CAN_F9R1_FB24_MskDWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)TIM_DIER_CC2DE TIM_DIER_CC2DE_MskDMA_LISR_HTIF0 DMA_LISR_HTIF0_MskRCC_APB1ENR_I2C1EN_Pos (21U)CAN_F3R1_FB29 CAN_F3R1_FB29_Msk_GLIBCXX_CXX_CONFIG_H 1SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk__cpp_lib_is_constant_evaluated 201811LCAN_TSR_TXOK1_Pos (9U)FSMC_PCR2_ECCPS_Pos (17U)ADC_CSR_EOC1 ADC_CSR_EOC1_MskconfigMAX(a,b) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)CAN_F4R2_FB13_Pos (13U)SPI_SR_CHSIDE_Pos (2U)DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)CAN_F10R2_FB16_Pos (16U)LL_GPIO_PIN_2 GPIO_BSRR_BS_2ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolderRTC_ALRMBR_DT_Pos (28U)ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)I2C3_ER_IRQnUSB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)FSMC_BCR4_MUXEN_Pos (1U)LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0)EXTI_IMR_MR6_Pos (6U)CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_MskRTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)FSMC_BCR4_MWID FSMC_BCR4_MWID_MskCAN_TSR_TERR2_Pos (19U)CAN_F1R2_FB12 CAN_F1R2_FB12_MskCAN_F2R2_FB4_Pos (4U)CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)RTC_BKP16R_Pos (0U)GPIO_PUPDR_PUPD8 0x00030000UGPIO_OSPEEDR_OSPEED10_0 0x00100000UCAN_F10R1_FB30_Pos (30U)DWT_FUNCTION_MATCHED_Pos 24USCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)USB_OTG_DIEPINT_TOC_Pos (3U)CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)FSMC_BCR3_MTYP FSMC_BCR3_MTYP_MskCAN_IER_WKUIE_Pos (16U)__CHAR8_TYPE__ unsigned charFSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)CAN_F5R1_FB15 CAN_F5R1_FB15_MskGPIO_OSPEEDR_OSPEED6 0x00003000UCAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)DMA_HISR_FEIF4 DMA_HISR_FEIF4_MskRTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)CAN_F13R1_FB22 CAN_F13R1_FB22_MskCRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)USB_OTG_PCGCCTL_GATECLK_Pos (1U)CAN_F12R1_FB17_Pos (17U)configPRIO_BITS __NVIC_PRIO_BITSCAN_F2R1_FB5_Pos (5U)SDIO_STA_DATAEND SDIO_STA_DATAEND_MskMPU_RASR_TEX_Pos 19ULL_TIM_DIER_CC4IE TIM_DIER_CC4IEconfigUSE_PREEMPTION 1FLASH_SR_PGAERR_Pos (5U)DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_MskETH_PTPTSSR_TSSEME_Pos (14U)__FLT32X_MAX_10_EXP__ 308pdFREERTOS_ERRNO_ETIMEDOUT 116ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk_STL_ITERATOR_H 1ETH_DMAOMR_RTC_64Bytes 0x00000000URTC_ALRMAR_MSK2_Pos (15U)EXTI_PR_PR1_Pos (1U)FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk__FLT_MIN__ 1.1754943508222875e-38FSCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)EXTI_EMR_EM5 EXTI_EMR_MR5ADC_CCR_DELAY_Pos (8U)MSN_BHEAP_H GPIO_IDR_IDR_0 GPIO_IDR_ID0FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)RTC_CR_REFCKON_Pos (4U)USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_MskGPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)__TQ_FBIT__ 127SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)__GNUCLIKE___TYPEOF 1USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_MskTIM_SR_CC2IF TIM_SR_CC2IF_MskpdFREERTOS_ERRNO_ENAMETOOLONG 91CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)DstAddressCAN_F0R1_FB23_Pos (23U)ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0__FLT32_DENORM_MIN__ 1.4012984643248171e-45F32TIM_DIER_CC4IE_Pos (4U)LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOPRCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)CAN_F5R2_FB28_Pos (28U)FLASH_OTP_BASE 0x1FFF7800UL__UINTMAX_TYPE__ long long unsigned int__lock_close_recursive(lock) __retarget_lock_close_recursive(lock)DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)_GLIBCXX_HAVE_MACHINE_PARAM_H 1DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)GPIO_MODER_MODER2 GPIO_MODER_MODER2_MskETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)LL_MPU_REGION_NUMBER7 0x07UFSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)__builtin_align_down(x,align) ((__typeof__(x))((x)&(~((align)-1))))CAN_RDL1R_DATA3_Pos (24U)DAC_DOR2_DACC2DOR_Pos (0U)CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)GPIO_MODER_MODER12_Pos (24U)RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)CAN_F0R1_FB17_Pos (17U)CAN_F6R2_FB20 CAN_F6R2_FB20_MskI2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk_ecstackCAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)CAN_F0R2_FB25 CAN_F0R2_FB25_MskCAN_F9R1_FB2_Pos (2U)FSMC_BTR2_DATAST FSMC_BTR2_DATAST_MskTIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_MskRTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)SDIO_DCOUNT_DATACOUNT_Pos (0U)__debugCAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)USB_OTG_GINTSTS_HPRTINT_Pos (24U)RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)CAN_F13R2_FB13_Pos (13U)CAN_F11R2_FB20_Pos (20U)CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)RTC_TSDR_MU_Pos (8U)CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)SCB_CCR_UNALIGN_TRP_Pos 3URCC_CIR_LSERDYC_Pos (17U)SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_MskSDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk_GLIBCXX_PTRDIFF_T_IS_INT 1ADC_CR2_DDS_Pos (9U)__try if (true)APSR_C_Msk (1UL << APSR_C_Pos)GPIO_ODR_OD6 0x00000040UTIM_CCMR2_OC3PE_Pos (3U)CAN_MSR_INAK_Pos (0U)__NO_RETURN __attribute__((__noreturn__))FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_MskRTC_TSDR_WDU RTC_TSDR_WDU_MskGPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)DAC_DHR12RD_DACC1DHR_Pos (0U)DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_MskUSB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)GPIOH ((GPIO_TypeDef *) GPIOH_BASE)_GLIBCXX_TXN_SAFE_DYN CAN_F2R1_FB27_Pos (27U)TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)GPIO_PUPDR_PUPD13 0x0C000000ULL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)FLASH_SR_WRPERR_Pos (4U)ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_MskUSB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_MskpdFREERTOS_ERRNO_ENODEV 19_REENT_MP_RESULT(ptr) ((ptr)->_result)SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)LL_TIM_WriteReg(__INSTANCE__,__REG__,__VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))CAN_F2R2_FB11 CAN_F2R2_FB11_MskETH_MMCTIR_TGFMSCS_Pos (15U)TIM_CR2_MMS TIM_CR2_MMS_MskUSB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)USB_OTG_DOEPINT_AHBERR_Pos (2U)configIDLE_SHOULD_YIELD 1ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_MskUSB_OTG_DOEPCTL_NAKSTS_Pos (17U)GPIO_AFRL_AFSEL1 0x000000F0UCAN_F11R2_FB2 CAN_F11R2_FB2_MskRCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_MskCAN_F13R2_FB30_Pos (30U)RCC_APB1ENR_TIM6EN_Pos (4U)TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)RCC_SSCGR_INCSTEP_Pos (13U)_REENT_CHECK_EMERGENCY(ptr) USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_MskUSB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)ETH_MACDBGR_TFRS_Pos (20U)DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_MskCAN_FM1R_FBM27_Pos (27U)GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3pdPASS ( pdTRUE )CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)CAN_TSR_LOW1 CAN_TSR_LOW1_MskPWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)__UINT_LEAST64_TYPE__ long long unsigned intGPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)TPI_TRIGGER_TRIGGER_Msk (0x1UL )GPIO_MODER_MODE1 0x0000000CUADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)CAN_F1R2_FB13_Pos (13U)CAN_F0R2_FB5_Pos (5U)USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)__DBL_MIN_EXP__ (-1021)ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)USART_CR3_HDSEL USART_CR3_HDSEL_Msk__NULLABILITY_PRAGMA_PUSH ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)__LONG_MAX__ 0x7fffffffLRCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)__cpp_lib_clamp 201603L__cpp_concepts 202002LCAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)GPIO_PUPDR_PUPD13_1 0x08000000U_GLIBCXX_THROW(_EXC) _GLIBCXX_CAN_ALIGNAS_DESTRUCTIVE_SIZE 1USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_MskCAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)TIM_DIER_CC1IE TIM_DIER_CC1IE_MskRCC_CR_HSITRIM RCC_CR_HSITRIM_MskPWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)RCC_AHB1RSTR_GPIOBRST_Pos (1U)RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_MskCAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_MskETH_MACSR_MMMCRS_Pos (5U)EXTI_IMR_MR7 EXTI_IMR_MR7_MskSDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)_CLOCKID_T_ unsigned longRTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)CAN_IER_ERRIE_Pos (15U)SRAM_BB_BASE SRAM1_BB_BASEUSB_OTG_HPRT_PENA_Pos (2U)FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)CAN_F12R2_FB29 CAN_F12R2_FB29_MskDWT_CTRL_CYCTAP_Pos 9UGPIO_OSPEEDR_OSPEED13 0x0C000000UTIM_CCER_CC3E TIM_CCER_CC3E_MskTIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)CAN_F3R2_FB23_Pos (23U)USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_MskLL_TIM_SR_COMIF TIM_SR_COMIFTIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk___int32_t_defined 1USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_MskUSB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_MskLL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)CAN_TI1R_EXID_Pos (3U)LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)LL_GPIO_PIN_1 GPIO_BSRR_BS_1CAN2_RX0_IRQnADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)__pure2 __attribute__((__const__))_GLIBCXX_HAVE_STRINGS_H 1USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_MskRTC_ISR_TAMP1F_Pos (13U)EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)CAN_F9R1_FB6 CAN_F9R1_FB6_MskCAN_F5R1_FB22 CAN_F5R1_FB22_MskFSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)__QQ_IBIT__ 0_GLIBCXX_STDIO_SEEK_CUR 1CAN_FS1R_FSC12_Pos (12U)FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)I2C_CR2_ITERREN_Pos (8U)USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)DCMI_SR_FNE DCMI_SR_FNE_MskCAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)ETH_DMAOMR_TTC_Pos (14U)FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)CAN_F8R2_FB29 CAN_F8R2_FB29_MskCAN_ESR_EWGF CAN_ESR_EWGF_MskRTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)GPIO_OTYPER_OT1 0x00000002UETH_MACA3HR_MBC_LBits7_0 0x01000000USPI_SR_RXNE_Pos (0U)CAN_F3R2_FB17_Pos (17U)CAN_F1R2_FB24 CAN_F1R2_FB24_MskDMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_MskETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_MskADC_SMPR1_SMP17 ADC_SMPR1_SMP17_MskSDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)CoreDebug_DHCSR_S_RETIRE_ST_Pos 24URCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_MskDCMI_IER_LINE_IE_Pos (4U)RTC_BKP2R_Pos (0U)TypeSetCalibrationUSB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)INT_LEAST32_MIN (-INT_LEAST32_MAX - 1)RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_MskSTM32F2 LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)CAN_F11R2_FB24 CAN_F11R2_FB24_MskxPSR_C_Msk (1UL << xPSR_C_Pos)CoreDebug_DHCSR_S_REGRDY_Pos 16UCAN_FM1R_FBM27 CAN_FM1R_FBM27_MskGPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)FLASH_SR_BSY_Pos (16U)FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_MskADC_CCR_VBATE_Pos (22U)CAN_F8R1_FB8 CAN_F8R1_FB8_MskRCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)SDIO_STA_DBCKEND SDIO_STA_DBCKEND_MskFSMC_BWTR4_DATAST_4 (0x10UL << FSMC_BWTR4_DATAST_Pos)FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)CAN_F7R2_FB8 CAN_F7R2_FB8_MskLL_MPU_ACCESS_NOT_SHAREABLE 0x00UCAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)TIM_CCER_CC1NE_Pos (2U)DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk__GNUCLIKE_MATH_BUILTIN_RELOPS ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_MskCAN_F1R1_FB13 CAN_F1R1_FB13_MskMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))USART6_BASE (APB2PERIPH_BASE + 0x1400UL)RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_MskDCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_MskTIM_CCMR1_IC2F_Pos (12U)RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_MskRCC_APB2ENR_TIM8EN_Pos (1U)__glibcxx_max_exponent10(_Tp) __glibcxx_floating(_Tp, __FLT_MAX_10_EXP__, __DBL_MAX_10_EXP__, __LDBL_MAX_10_EXP__)RTC_TSDR_DT_Pos (4U)CAN_TSR_ABRQ2_Pos (23U)CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)DCMI_CR_FCRC_0 0x00000100URCC_CFGR_PPRE1_DIV2 0x00001000URCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)CAN_F4R2_FB25_Pos (25U)USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)__SOFTFP__ 1GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)SPI_CR1_SSM_Pos (9U)GPIO_ODR_ODR_2 GPIO_ODR_OD2ETH_MACMIIAR_PA ETH_MACMIIAR_PA_MskADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk_COMPARE USB_OTG_DSTS_ENUMSPD_Pos (1U)ETH_MACA1HR_SA_Pos (30U)SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_MskSYSCFG_EXTICR1_EXTI2_PB 0x00000100USDIO_RESP3_CARDSTATUS3_Pos (0U)LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFUCAN_F13R2_FB5_Pos (5U)SYSCFG_EXTICR1_EXTI0_PD 0x00000003UCAN_RDL1R_DATA1 CAN_RDL1R_DATA1_MskUSART_CR3_CTSE USART_CR3_CTSE_MskTIM_DIER_UDE TIM_DIER_UDE_MskLL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000UFSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)traceCREATE_MUTEX_FAILED() CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)GPIO_PUPDR_PUPD2 0x00000030UGPIOG ((GPIO_TypeDef *) GPIOG_BASE)RCC_APB1ENR_UART5EN_Pos (20U)TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk__FLT32X_IS_IEC_60559__ 1TIM_SR_CC3OF TIM_SR_CC3OF_MskFSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)CAN_RI1R_RTR CAN_RI1R_RTR_MskCAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)EXTI_FTSR_TR0 EXTI_FTSR_TR0_MskETH_DMAOMR_TTC_192Bytes 0x00008000UDMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk__CMSIS_GCC_USE_REG(r) "r" (r)__CORTEX_M (3U)CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)CAN_F10R2_FB14 CAN_F10R2_FB14_MskEXTI_EMR_MR19 EXTI_EMR_MR19_MskCAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_MskFSMC_SR4_ILEN FSMC_SR4_ILEN_MskLL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCENRCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_MskCAN_F0R1_FB6_Pos (6U)CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)CAN_F10R2_FB30_Pos (30U)ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)DMA_SxCR_CIRC DMA_SxCR_CIRC_MskCAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_MskRCC_CR_CSSON_Pos (19U)_GLIBCXX_HAVE_BUILTIN_LAUNDER 1USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)UI_BUTTON_PORT GPIOACAN_FFA1R_FFA9_Pos (9U)__USFRACT_IBIT__ 0FSMC_PCR4_PTYP_Pos (3U)ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)DMA_HISR_TEIF4_Pos (3U)SDIO_MASK_SDIOITIE_Pos (22U)ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)TIM_DIER_CC1IE_Pos (1U)RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)FSMC_PCR4_PWID FSMC_PCR4_PWID_MskFSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)__FLT32X_MANT_DIG__ 53SCB_AIRCR_VECTRESET_Msk (1UL )CCERCAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)SDIO_CLKCR_CLKDIV_Pos (0U)xDummy3USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_MskMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)GPIO_BSRR_BR_4 GPIO_BSRR_BR4DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk_Static_assert(x,y) static_assert(x, y)ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_MskWWDG_CR_T1 WWDG_CR_T_1FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)CAN_F10R2_FB24_Pos (24U)FSMC_BWTR1_ADDSET_Pos (0U)__ACCUM_MIN__ (-0X1P15K-0X1P15K)CAN_FM1R_FBM6 CAN_FM1R_FBM6_MskUSB_OTG_DOEPINT_OTEPSPR_Pos (5U)SCnSCB ((SCnSCB_Type *) SCS_BASE )FSMC_PCR3_PTYP FSMC_PCR3_PTYP_MskTIM1_BASE (APB2PERIPH_BASE + 0x0000UL)APSR_Q_Pos 27UCAN_F6R1_FB21 CAN_F6R1_FB21_MskUSB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)FSMC_R_BASE 0xA0000000ULRTC_TSDR_MT_Pos (12U)CAN_F0R1_FB26 CAN_F0R1_FB26_MskUSB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_MskCAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)ETH_MACA0HR_MACA0H_Pos (0U)CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_MskDMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)GPIO_OSPEEDR_OSPEED15 0xC0000000URTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_MskCAN_F9R2_FB28 CAN_F9R2_FB28_MskADC_CR2_JEXTEN ADC_CR2_JEXTEN_MskportPRE_TASK_DELETE_HOOK(pvTaskToDelete,pxYieldPending) CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_MskTIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)MEMRMP__CHAR_UNSIGNED__ 1CAN_F0R2_FB10 CAN_F0R2_FB10_MskSDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)portTickType TickType_tDWT_EXCCNT_EXCCNT_Msk (0xFFUL )__GNUC__ 13PWR_CSR_EWUP PWR_CSR_EWUP_MskCAN_F3R1_FB11 CAN_F3R1_FB11_MskDMA_HIFCR_CTEIF6_Pos (19U)_GLIBCXX_HAVE_STDBOOL_H 1LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)CAN_TSR_CODE CAN_TSR_CODE_MskFLASH_CR_STRT_Pos (16U)FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)SYSCFG_EXTICR3_EXTI11_Pos (12U)ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_MskCAN_F6R1_FB1 CAN_F6R1_FB1_MskFSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)CAN_F7R1_FB3_Pos (3U)CAN_FS1R_FSC4_Pos (4U)DCMI_SR_FNE_Pos (2U)CAN_F3R1_FB10_Pos (10U)SYSCFG_EXTICR2_EXTI4_PA 0x00000000UETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)GPIO_ODR_OD12 0x00001000UCAN_F8R2_FB20_Pos (20U)I2C_SR1_BTF I2C_SR1_BTF_MskCAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)USART_CR3_HDSEL_Pos (3U)CAN_F9R1_FB17 CAN_F9R1_FB17_MskCAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)SDIO_MASK_DTIMEOUTIE_Pos (3U)TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)_GLIBCXX_ABI_TAG_CXX11 __attribute ((__abi_tag__ ("cxx11")))FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)CAN_F2R1_FB12 CAN_F2R1_FB12_MskI2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)RTC_CR_BKP_Pos (18U)I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)DMA_HISR_DMEIF5_Pos (8U)traceQUEUE_PEEK(pxQueue) FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_MskDAC_CR_BOFF1 DAC_CR_BOFF1_MskADC_SR_JSTRT ADC_SR_JSTRT_MskRCC_CSR_RMVF RCC_CSR_RMVF_Mskalloca__ARM_NEON_FPCAN_F5R2_FB19 CAN_F5R2_FB19_MskconfigQUEUE_REGISTRY_SIZE 0USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)RCC_APB1ENR_TIM3EN_Pos (1U)GPIO_BSRR_BR_12 GPIO_BSRR_BR12CAN_F12R2_FB28_Pos (28U)DMA1_Stream6_IRQnRCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk_GLIBCXX_VERBOSE_ASSERT 1FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)print_wrapped_linesCAN_F5R1_FB3 CAN_F5R1_FB3_MskTypeSyncUSB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)_GLIBCXX_THROW_OR_ABORT(_EXC) (__builtin_abort())CAN_F4R2_FB3 CAN_F4R2_FB3_MskDCMI_ESUR_FSU DCMI_ESUR_FSU_MskCAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPENportCRITICAL_NESTING_IN_TCB 0_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)DIERRCC_APB2RSTR_ADCRST_Pos (8U)CAN_F10R2_FB3 CAN_F10R2_FB3_MskCAN_F4R2_FB5_Pos (5U)RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)CAN_F1R2_FB31 CAN_F1R2_FB31_MskFSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)ETH_MACFFR_PAM ETH_MACFFR_PAM_MskETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)CAN_MCR_NART_Pos (4U)__SYS_LOCK_H__ __cpp_lib_is_layout_compatible 201907LWWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)_GLIBCXX17_CONSTEXPR constexprGrabberIDRCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)ADC_SR_STRT_Pos (4U)CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)SYSCFG_EXTICR3_EXTI8_PB 0x00000001UCAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_MskRTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)CAN_F3R1_FB12_Pos (12U)__glibcxx_requires_irreflexive2(_First,_Last) RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)LL_FLASH_DisableDataCacheRCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)CAN_F13R1_FB14 CAN_F13R1_FB14_MskCAN_F13R1_FB4 CAN_F13R1_FB4_MskTIM_CR2_CCUS_Pos (2U)USB_OTG_DPID USB_OTG_DPID_MskxPSR_ICI_IT_1_Pos 10UCAN_FA1R_FACT16_Pos (16U)ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)DCMI_CR_VSPOL_Pos (7U)pdFREERTOS_ERRNO_EXDEV 18TPI_ITATBCTR2_ATREADY2_Msk (0x1UL )CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)GPIO_OSPEEDR_OSPEED8 0x00030000URCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)11RTC_TypeDefRTC_ISR_ALRAF_Pos (8U)SRV_H SDIO_DCTRL_DTMODE_Pos (2U)ADC_SQR2_SQ7 ADC_SQR2_SQ7_MskSDIO_DCTRL_DTDIR_Pos (1U)_GLIBCXX_HAVE_SQRTF 1I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_MskCAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)___int64_t_defined 1portALLOCATE_SECURE_CONTEXT(ulSecureStackSize) SPI_SR_OVR_Pos (6U)GPIO_MODER_MODE11_1 0x00800000UCAN_F5R1_FB22_Pos (22U)RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)LL_TIM_DisableARRPreloadEXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)__USA_IBIT__ 16CAN_F5R1_FB4_Pos (4U)USB_OTG_HCINT_AHBERR_Pos (2U)LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_MskUSB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_MskSPI1 ((SPI_TypeDef *) SPI1_BASE)PWR_CR_FPDS PWR_CR_FPDS_MskCAN_F10R2_FB0_Pos (0U)SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_MskUART_DMA_TX_Stream LL_DMA_STREAM_7USART_CR1_PEIE USART_CR1_PEIE_MskRCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)traceSTREAM_BUFFER_RECEIVE_FAILED(xStreamBuffer) ETH_MACA3HR_MBC_HBits7_0 0x10000000URCC_APB1RSTR_TIM6RST_Pos (4U)__cpp_lib_bounded_array_traits 201902LCAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)_RANGES_ALGO_H 1__FLT64_HAS_INFINITY__ 1CAN_F5R1_FB16_Pos (16U)FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)traceEVENT_GROUP_WAIT_BITS_BLOCK(xEventGroup,uxBitsToWaitFor) TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)SPI_CRCPR_CRCPOLY_Pos (0U)__SACCUM_MAX__ 0X7FFFP-7HKCAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)USB_OTG_DIEPCTL_SODDFRM_Pos (29U)CAN_F6R2_FB13 CAN_F6R2_FB13_MskLL_SYSCFG_EXTI_PORTF (uint32_t)5ETH_MACDBGR_RFRCS_IDLE 0x00000000UFSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)DCMI_CR_ESS DCMI_CR_ESS_MskCAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)CAN_FA1R_FACT1 CAN_FA1R_FACT1_MskpxDummy1__FLT64_MIN_EXP__ (-1021)pxDummy6ETH_DMAOMR_TTC_40Bytes 0x00010000UFSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk__cpp_lib_char8_t 201907LUSB_OTG_DSTS_SUSPSTS_Pos (0U)RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1__DBL_HAS_INFINITY__ 1GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_MskSYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_MskSPI_CR2_ERRIE SPI_CR2_ERRIE_MskEXTI_IMR_MR11 EXTI_IMR_MR11_MskCAN_F7R1_FB26_Pos (26U)ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)RCC_PLLCFGR_PLLN_Pos (6U)CAN_F13R1_FB12_Pos (12U)CRC_CR_RESET CRC_CR_RESET_MskCAN_RDH1R_DATA6 CAN_RDH1R_DATA6_MskCAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_MskCAN_F8R2_FB2_Pos (2U)MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)CAN_MCR_ABOM CAN_MCR_ABOM_MskUSB_OTG_HCSPLT_SPLITEN_Pos (31U)ETH_MACA3HR_MBC ETH_MACA3HR_MBC_MskGPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)MS_FREERTOS_CONFIG_H EXTI_SWIER_SWIER12_Pos (12U)CAN_F2R2_FB30 CAN_F2R2_FB30_MskDWT_MASK_MASK_Pos 0UADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)SPI_CR1_BIDIOE SPI_CR1_BIDIOE_MskUSB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_MskFSMC_PATT3_ATTWAIT3_Pos (8U)RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")SLOTS_H ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)EXTI_EMR_MR8_Pos (8U)USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)RTC_TR_MNU RTC_TR_MNU_MskCAN_F6R2_FB12_Pos (12U)__STM32F2xx_CMSIS_VERSION_RC (0x00U)USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)ADC_CSR_OVR1 ADC_CSR_OVR1_MskUSB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)__nonnull(x) __attribute__((__nonnull__ x))__LL_TIM_CALC_DELAY(__TIMCLK__,__PSC__,__DELAY__) ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_MskGPIO_BSRR_BR1 0x00020000UCAN1_RX0_IRQnLL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_MskRTC_DR_DT_Pos (4U)xPSR_ISR_Pos 0UFSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk_GLIBCXX_BEGIN_INLINE_ABI_NAMESPACE(X) inline namespace X {CAN_ESR_BOFF_Pos (2U)USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_MskTIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)ETH_MACFFR_PCF ETH_MACFFR_PCF_MskEXTI_PR_PR7 EXTI_PR_PR7_MskDMA_SxCR_CIRC_Pos (8U)ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)__UINT64_TYPE__ long long unsigned intDMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_MskETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)RTC_BKP14R RTC_BKP14R_Msk/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/build_nucleoCAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)EXTI_IMR_MR15_Pos (15U)RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk__INTMAX_WIDTH__ 64SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)LL_GPIO_PULL_NO (0x00000000U)GPIO_MODER_MODER3_Pos (6U)CAN_F12R2_FB22 CAN_F12R2_FB22_MskSDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_MskFSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)CAN_F0R2_FB0 CAN_F0R2_FB0_MskETH_DMASR_ROS_Pos (4U)CAN_F8R2_FB22_Pos (22U)__MISC_VISIBLE 1USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_MskDMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3DMA_SxM0AR_M0A_Pos (0U)EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)CAN_F12R1_FB23_Pos (23U)RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)USB_OTG_DIEPMSK_EPDM_Pos (1U)__glibcxx_requires_partitioned_lower_pred(_First,_Last,_Value,_Pred) TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)ADC_CR1_RES ADC_CR1_RES_MskUSB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)USB_OTG_GRSTCTL_CSRST_Pos (0U)USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)SYSCFG_EXTICR2_EXTI5_PC 0x00000020UCAN_RDT1R_FMI_Pos (8U)configUSE_TASK_NOTIFICATIONS 1CAN_F8R2_FB16_Pos (16U)ETH_DMABMR_SR ETH_DMABMR_SR_MskFSMC_PATT2_ATTSET2_Pos (0U)CAN_F7R2_FB12 CAN_F7R2_FB12_MskETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)_ANSI_STDDEF_H USART_CR3_EIE USART_CR3_EIE_MskCAN_F10R1_FB2 CAN_F10R1_FB2_MskUSART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)__LL_TIM_CALC_PSC(__TIMCLK__,__CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2INTMAX_MAX __INTMAX_MAX__RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)FSMC_BTR3_ACCMOD_Pos (28U)FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk_REENT_SIGNAL_SIZE 24CAN_TI2R_IDE_Pos (2U)USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)STM_HEAP_SIZE (13*1024)tim_initCAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3ENFSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)GPIO_LCKR_LCK2_Pos (2U)FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASECAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)DMA_LISR_DMEIF1_Pos (8U)pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aULOTG_FS_WKUP_IRQnUSB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)FLASH_IRQnCAN_F2R1_FB16_Pos (16U)CAN_FM1R_FBM22_Pos (22U)DMA_HISR_HTIF7_Pos (26U)FLASH_CR_PSIZE_Pos (8U)CAN_F2R2_FB0 CAN_F2R2_FB0_Msk_NEWLIB_ALLOCA_H _ZN3srv8Servicer11PendRequest18CalibrationRequestD4EvDWT_CPICNT_CPICNT_Msk (0xFFUL )USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)ETH_MACA3HR_MBC_LBits15_8 0x02000000UCCR1CCR2CCR3CCR4__UINT64_MAX__ 0xffffffffffffffffULLADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)__INT_FAST64_TYPE__ long long intUSB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_MskTIM_CCER_CC1E_Pos (0U)FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)ETH_MACDBGR_RFFL_EMPTY 0x00000000UCAN_FM1R_FBM16_Pos (16U)traceQUEUE_PEEK_FROM_ISR_FAILED(pxQueue) __ARM_FEATURE_AESCAN_F8R1_FB19_Pos (19U)CAN_FFA1R_FFA24_Pos (24U)SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))CAN_F4R1_FB26_Pos (26U)USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)TIM_EGR_CC2G_Pos (2U)_REENT_SMALL_CHECK_INIT(ptr) traceEVENT_GROUP_SET_BITS_FROM_ISR(xEventGroup,uxBitsToSet) RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_MskADC_JDR1_JDATA_Pos (0U)DCMI_MIS_OVR_MIS_Pos (1U)CAN_F11R2_FB7_Pos (7U)GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2CAN_F4R1_FB28 CAN_F4R1_FB28_MskCAN_F12R1_FB5 CAN_F12R1_FB5_MsktaskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )USB_OTG_DCTL_SGONAK_Pos (9U)__cpp_aggregate_bases 201603LUSB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)TIM_CCR3_CCR3_Pos (0U)CAN_FFA1R_FFA18_Pos (18U)FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3)RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)__GNUCLIKE_BUILTIN_MEMCPY 1_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)FLASH_ACR_BYTE0_ADDRESS_Pos (10U)_PSTL_STRING(x) _PSTL_STRING_AUX(x)ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_MskFSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2ENCAN_F5R1_FB26 CAN_F5R1_FB26_MskADC_CR2_JSWSTART_Pos (22U)TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)GPIO_OSPEEDR_OSPEED2 0x00000030URCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)CAN_F3R2_FB12_Pos (12U)LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)ADC_CR1_JEOCIE ADC_CR1_JEOCIE_MskuxDummy12LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0CALIBRUSB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk__always_inline __inline__ __attribute__((__always_inline__))CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk__QQ_FBIT__ 7ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)CAN_TSR_TME2 CAN_TSR_TME2_MsklistGET_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext )EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_MskFLASH_CR_EOPIE FLASH_CR_EOPIE_MskCAN_F10R2_FB29_Pos (29U)CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)_GLIBCXX_HAVE_WCTYPE_H 1CAN_F0R1_FB19 CAN_F0R1_FB19_Msk_GLIBCXX20_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)SPI_CR1_BIDIOE_Pos (14U)INT16_MINDMA_LIFCR_CFEIF0_Pos (0U)LL_SYSCFG_EXTI_PORTA (uint32_t)0DWT_FUNCTION_EMITRANGE_Pos 5UCAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)ITM_TCR_TSENA_Pos 1UGPIO_LCKR_LCK15 GPIO_LCKR_LCK15_MskUSB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)USB_OTG_GINTSTS_IISOIXFR_Pos (20U)CAN_F2R2_FB16 CAN_F2R2_FB16_MskDAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_MskLL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)EXTI_IMR_IM0 EXTI_IMR_MR0FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)EXTI_FTSR_TR10_Pos (10U)FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)SYSCFG_EXTICR3_EXTI11_PI 0x00008000UDMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)CAN_F2R1_FB26 CAN_F2R1_FB26_MskGPIO_OTYPER_OT_11 GPIO_OTYPER_OT11DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RISETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_MskDMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)USB_OTG_HPRT_PRST_Pos (8U)FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)_NOTHROW __attribute__ ((__nothrow__))RCC_APB2LPENR_TIM11LPEN_Pos (18U)RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)PWR_CR_DBP_Pos (8U)LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_MskEXTI_PR_PR4 EXTI_PR_PR4_MskETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_MskCAN_F3R2_FB4_Pos (4U)FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_MskFSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)AHB2LPENRMPU_RASR_XN_Pos 28URCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_MskRCC_APB2RSTR_SDIORST_Pos (11U)CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_MskUSB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_MskCAN_F5R2_FB16_Pos (16U)CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk_ZN5crash14panic_from_isrEPKcPmCAN_F11R1_FB17 CAN_F11R1_FB17_MskItemTypeI2C_SR2_SMBHOST_Pos (6U)ETH_DMABMR_PBL_4Beat 0x00000400URCC_CR_HSEON_Pos (16U)FSMC_BTR1_DATAST FSMC_BTR1_DATAST_MskCAN_F2R1_FB31 CAN_F2R1_FB31_MskCoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)timestamp_outPendRequestLL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)DAC_CR_EN2 DAC_CR_EN2_MskCAN_RDH1R_DATA4_Pos (0U)ADC_SMPR1_SMP17_Pos (21U)USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)BSRRFSMC_BWTR1_ADDHLD_Pos (4U)CAN_F6R2_FB3_Pos (3U)__SA_IBIT__ 16TIM_CCMR2_IC3F_Pos (4U)SYSCFG_EXTICR3_EXTI11_PC 0x00002000UARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)SDIO_STA_RXACT_Pos (13U)ADC_SR_JSTRT_Pos (3U)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__PWR_CR_PLS_LEV1 0x00000020UCAN_F8R1_FB11_Pos (11U)CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)traceTAKE_MUTEX_RECURSIVE(pxMutex) ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)CAN_F7R2_FB26_Pos (26U)ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)CAN_TDT0R_TIME CAN_TDT0R_TIME_MskFLASH_SR_SOP FLASH_SR_SOP_MskCAN_F11R1_FB27_Pos (27U)DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)SYSCFG_EXTICR2_EXTI4_PC 0x00000002UGPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)CAN_F10R1_FB12 CAN_F10R1_FB12_MskDCMI_DR_BYTE1_Pos (8U)FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)_ZN5crash6decode15resolve_symbolsEPA100_cPKmtRTC_CR_WUTE_Pos (10U)ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)ETH_DMAIER_TPSIE_Pos (1U)WWDG_CR_T4 WWDG_CR_T_4DCMI_ESUR_FEU DCMI_ESUR_FEU_MskETH_MACMIIAR_MW_Pos (1U)CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)FSMC_PMEM4_MEMSET4_Pos (0U)USB_OTG_GINTMSK_USBRST_Pos (12U)IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))TIM_CCER_CC2E_Pos (4U)__USFRACT_FBIT__ 8EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_MskCAN_F10R2_FB10_Pos (10U)FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_MskIS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8))__UINT_FAST32_MAX__ 0xffffffffUTIM_CCMR1_IC1F TIM_CCMR1_IC1F_MskFSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)ITM_LSR_Access_Pos 1UCAN_F3R2_FB10 CAN_F3R2_FB10_MskCAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)LL_MPU_ACCESS_NOT_CACHEABLE 0x00UDMA_HISR_TCIF6 DMA_HISR_TCIF6_MskPWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)___int_ptrdiff_t_h USB_OTG_HPRT_PRES_Pos (6U)EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)__unbounded NVIC_BASE (SCS_BASE + 0x0100UL)RCC_AHB1RSTR_ETHMACRST_Pos (25U)ADC_CSR_OVR1_Pos (5U)GPIO_MODER_MODE11 0x00C00000URTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)ETH_MACA3LR_MACA3L_Pos (0U)__UINT8_MAX__ 0xffCAN_F7R1_FB13 CAN_F7R1_FB13_MskUSART2_IRQnSPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)__GCC_ATOMIC_CHAR8_T_LOCK_FREE 2_PSTL_STRING_CONCAT(x,y) x #ySYSCFG_EXTICR1_EXTI2_PD 0x00000300UCAN_FFA1R_FFA7 CAN_FFA1R_FFA7_MskTIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)ADC_LTR_LT_Pos (0U)USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)CAN_MCR_TXFP_Pos (2U)_GLIBCXX_HAVE_LIMIT_DATA 0CAN_F9R2_FB1 CAN_F9R2_FB1_MskRCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)RTC_TSTR_HT_Pos (20U)traceEND() MPU_CTRL_ENABLE_Pos 0UTIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)RCC_CSR_PORRSTF_Pos (27U)LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFUSYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCENCAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)BKP10RUSB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)_GLIBCXX_ITERATOR 1GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)ETH_DMASR_RPS_Closing_Pos (17U)ETH_MACDBGR_TFRS_IDLE 0x00000000UFSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)CAN_F12R2_FB23_Pos (23U)DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)DWT_EXCCNT_EXCCNT_Pos 0UFSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14__LOCK_INIT(class,lock) extern struct __lock __lock_ ## lock; class _LOCK_T lock = &__lock_ ## lockFSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)ETH_MMCCR_MCP ETH_MMCCR_MCP_MskLL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)__ARM_FEATURE_BF16_VECTOR_ARITHMETICCAN_F9R1_FB3 CAN_F9R1_FB3_MskCAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)SYSCFG_EXTICR1_EXTI0_PC 0x00000002UUSB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)CAN_F8R2_FB3 CAN_F8R2_FB3_MskLL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_MskI2C_CR1_ENPEC I2C_CR1_ENPEC_MskCAN_F2R2_FB2_Pos (2U)_GLIBCXX11_USE_C99_WCHAR 1DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_MskEXTI_FTSR_TR5 EXTI_FTSR_TR5_MskARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)_T_PTRDIFF CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)BKP11RTIM_CR1_OPM_Pos (3U)IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1CAN_F13R2_FB13 CAN_F13R2_FB13_MskI2C_CR1_NOSTRETCH_Pos (7U)CAN_F12R2_FB17_Pos (17U)SYSCFG_EXTICR4_EXTI12_PD 0x00000003UCAN_F3R1_FB5_Pos (5U)DCMI_MIS_VSYNC_MIS_Pos (3U)FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)__FLT64_MAX_EXP__ 1024RCC_CFGR_SW_PLL 0x00000002UINT_FAST8_MIN (-INT_FAST8_MAX - 1)RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECEIS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE) || ((INSTANCE) == GPIOF) || ((INSTANCE) == GPIOG) || ((INSTANCE) == GPIOH) || ((INSTANCE) == GPIOI))SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)_GLIBCXX_HAVE_IEEEFP_H 1ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)CAN_F12R1_FB31 CAN_F12R1_FB31_MskUSB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)USB_OTG_GOTGCTL_CIDSTS_Pos (16U)LL_MPU_REGION_NUMBER2 0x02UI2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)DAC_CR_DMAUDRIE2_Pos (29U)CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)GPIO_ODR_OD2 0x00000004U_REENT _impure_ptrUSB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_MskCAN_F2R2_FB23 CAN_F2R2_FB23_MskFLASH_ACR_LATENCY_4WS 0x00000004U__cust_swapTIM_SMCR_MSM TIM_SMCR_MSM_MskCAN_F11R1_FB30 CAN_F11R1_FB30_MskRCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_MskCAN_F10R1_FB0_Pos (0U)EXTI_EMR_MR5_Pos (5U)USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)FLASH_CR_PG_Pos (0U)ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)__glibcxx_floatingUSART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_MskCAN_F6R1_FB4_Pos (4U)CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)ETH_MACDBGR_RFWRA_Pos (4U)USB_OTG_GOTGCTL_HNPRQ_Pos (9U)FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_MskCAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)RCC_CFGR_HPRE_DIV8 0x000000A0USYSCFG_EXTICR2_EXTI4_PD 0x00000003UCAN_F0R2_FB23_Pos (23U)SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_MskADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)USART_SR_CTS_Pos (9U)RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_MskADC_CSR_JEOC2_Pos (10U)USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)_GLIBCXX_HAVE_VWSCANF 1LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)GPIO_IDR_IDR_3 GPIO_IDR_ID3LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3ENETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_MskETH_DMASR_RPSS_Pos (8U)CAN_F11R1_FB6 CAN_F11R1_FB6_MskSCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)USB_OTG_GINTSTS_PTXFE_Pos (26U)TaskHolder<176>FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_MskLL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3ENCAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)CAN_FFA1R_FFA_Pos (0U)traceQUEUE_SEND_FAILED(pxQueue) RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)CAN_FM1R_FBM24_Pos (24U)xTaskNotifyFromISR(xTaskToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)__UTQ_FBIT__ 128CAN_F5R1_FB11_Pos (11U)GPIO_MODER_MODE6_0 0x00001000UEXTI_EMR_EM18 EXTI_EMR_MR18RNG_SR_SECS RNG_SR_SECS_MskCAN_TDL0R_DATA3 CAN_TDL0R_DATA3_MskI2C_OAR1_ADD8_Pos (8U)TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)ADC2 ((ADC_TypeDef *) ADC2_BASE)__cpp_variable_templates 201304L_GLIBCXX_HAVE_LOCALE_H 1SPI_DR_DR SPI_DR_DR_MskCAN_FA1R_FACT22_Pos (22U)CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)traceSTREAM_BUFFER_RECEIVE_FROM_ISR(xStreamBuffer,xReceivedLength) LL_GPIO_AF_1 (0x0000001U)CAN_F12R2_FB7_Pos (7U)RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk__ARM_SIZEOF_WCHAR_T 4SYSCFG_EXTICR3_EXTI8_PE 0x00000004UCAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)TIM_CCER_CC3E_Pos (8U)USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)CAN_RDT0R_FMI_Pos (8U)LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WSLL_TIM_CHANNEL_CH2 TIM_CCER_CC2EI2C_OAR1_ADD5_Pos (5U)FSMC_BCR2_WAITPOL_Pos (9U)CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)EXTI_SWIER_SWIER5_Pos (5U)FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)CAN_F2R2_FB27_Pos (27U)__predict_true(exp) __builtin_expect((exp), 1)xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)INT64_C(c) __INT64_C(c)protocolLL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0)SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_MskCAN_RF1R_RFOM1_Pos (5U)CAN_F7R1_FB21_Pos (21U)DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)NVIC_SRV_RX_IRQ_HANDLER DMA2_Stream1_IRQHandlerTIM_CCER_CC1P TIM_CCER_CC1P_MskDCMI_RIS_LINE_RIS_Pos (4U)FLASH_OTP_END 0x1FFF7A0FULCAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)BKP15RCAN_F7R2_FB31 CAN_F7R2_FB31_MskCAN_FS1R_FSC25 CAN_FS1R_FSC25_MskRCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_MskFSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)ETH_DMASR_TPS_Fetching_Pos (20U)ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_MskCoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)__FLT64_MIN__ 2.2250738585072014e-308F64ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)xPSR_Z_Pos 30URCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_MskCAN_F7R1_FB15_Pos (15U)__ALIGNED(x) __attribute__((aligned(x)))LL_TIM_TS_ITR2 TIM_SMCR_TS_1RCC_AHB1LPENR_DMA2LPEN_Pos (22U)LL_DMA_SetMemoryIncModeLL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SELCoreDebug_DEMCR_VC_HARDERR_Pos 10UADC_CCR_MULTI_Pos (0U)_PSTL_PRAGMA_VECTOR_UNALIGNED CAN_F13R1_FB9 CAN_F13R1_FB9_MskCAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_MskOFFSET_TAB_CCMRxMPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)CAN_F9R1_FB31_Pos (31U)TIM_ARR_ARR TIM_ARR_ARR_MskCAN_F2R1_FB0_Pos (0U)CAN_F7R1_FB20 CAN_F7R1_FB20_MskUSB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)ETH_PTPTSCR_TSSTU_Pos (3U)CAN_F1R1_FB25 CAN_F1R1_FB25_MskDMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_MskSCB_ICSR_VECTPENDING_Pos 12UCAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)SEMAPHORE_H LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)CAN_F3R2_FB22 CAN_F3R2_FB22_MskRCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_MskportNOP() _GLIBCXX_HAVE_LOGF 1CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)ETH_MACHTLR_HTL_Pos (0U)RCC_CSR_LPWRRSTF_Pos (31U)SDIO_ICR_CEATAENDC_Pos (23U)USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_MskETH_MACDBGR_MTP_Pos (19U)CAN_F1R2_FB9 CAN_F1R2_FB9_MskCAN_F9R1_FB25_Pos (25U)TIM_SMCR_TS TIM_SMCR_TS_MskCAN_F4R2_FB4_Pos (4U)CAN_F2R2_FB26_Pos (26U)BKP17RSYSCFG_EXTICR1_EXTI2_PE 0x00000400UCAN_TI0R_EXID CAN_TI0R_EXID_MskEXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_MskCAN_BTR_SJW CAN_BTR_SJW_MskCAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0FSMC_BTR3_CLKDIV_Pos (20U)FSMC_SR4_IFS FSMC_SR4_IFS_MskEXTI_PR_PR22 EXTI_PR_PR22_MskCAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)ETH_DMAMFBOCR_MFA_Pos (17U)RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_MskFSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)CAN_TI2R_EXID_Pos (3U)SCB_AIRCR_PRIGROUP_Pos 8UCAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)RTC_BKP14R_Pos (0U)CAN_F4R2_FB0 CAN_F4R2_FB0_MskFSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)CAN_F11R1_FB12_Pos (12U)__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ARM_MPU_ARMV7_H ADC_CR1_JAWDEN ADC_CR1_JAWDEN_MskETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk_GLIBCXX_NOEXCEPT_PARM , bool _NEtraceTIMER_CREATE_FAILED() SDIO_STA_RXOVERR_Pos (5U)CAN_F9R1_FB19_Pos (19U)PORTABLE_H LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1USART_CR1_IDLEIE_Pos (4U)CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)CAN_F6R2_FB18 CAN_F6R2_FB18_MskEXTI_EMR_EM11 EXTI_EMR_MR11BKP18RUSB_OTG_GINTMSK_PRTIM_Pos (24U)GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)WCHAR_MAX __WCHAR_MAX__USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)ETH_DMASR_RWTS ETH_DMASR_RWTS_MskUSB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)USART_CR2_LINEN_Pos (14U)FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_MskSDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_MskGPIO_MODER_MODER9 GPIO_MODER_MODER9_MskCAN_F12R1_FB12_Pos (12U)ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk_ZN5crash4rtos24guess_active_thread_nameEvADC_CSR_EOC1_Pos (1U)CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_MskCAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)CAN_F11R2_FB27_Pos (27U)I2C_CR1_ACK_Pos (10U)SDIO_STA_CMDACT_Pos (11U)USART_CR1_TXEIE_Pos (7U)RCC_APB1RSTR_TIM4RST_Pos (2U)traceCREATE_COUNTING_SEMAPHORE_FAILED() configCPU_CLOCK_HZ (F_CPU)SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)FLASH_ACR_ICRST FLASH_ACR_ICRST_MskEXTI_EMR_EM15 EXTI_EMR_MR15CAN_TI2R_RTR CAN_TI2R_RTR_MskBKP19RCAN_F4R1_FB2 CAN_F4R1_FB2_MskCAN_F3R2_FB25 CAN_F3R2_FB25_MskFSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)EXTI_FTSR_TR17 EXTI_FTSR_TR17_MskI2C_CR1_SMBUS I2C_CR1_SMBUS_Msk_GLIBCXX_FULLY_DYNAMIC_STRING 0ETH_MMCRFAECR_RFAEC_Pos (0U)CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)EXTI_IMR_MR21_Pos (21U)GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)CAN_F12R1_FB8_Pos (8U)USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_MskGPIO_ODR_ODR_13 GPIO_ODR_OD13CAN_F4R1_FB27 CAN_F4R1_FB27_MskFSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)_PSTL_GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)CAN_F12R2_FB26 CAN_F12R2_FB26_MskSYSCFG_EXTICR3_EXTI8_Pos (0U)NVIC_SetVector __NVIC_SetVectorCAN_TDH2R_DATA5_Pos (8U)FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)__SFRACT_MIN__ (-0.5HR-0.5HR)SysTick_CALIB_TENMS_Pos 0UCAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)__flexarr [0]DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_MskUSB_OTG_FIFO_BASE 0x1000ULI2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)GPIO_AFRL_AFSEL7 0xF0000000U_REENT_STDIN(_ptr) ((_ptr)->_stdin)GPIO_MODER_MODE10 0x00300000UCAN_TSR_LOW1_Pos (30U)EXTI_PR_PR15 EXTI_PR_PR15_MskRTC_TSTR_PM RTC_TSTR_PM_MskDBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)CAN_F1R1_FB0 CAN_F1R1_FB0_MskGPIO_MODER_MODE7 0x0000C000UINT32_MINTIM_CCMR1_OC2M TIM_CCMR1_OC2M_MskLL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)__cpp_lib_array_constexpr 201811LulDummy18CAN_RDL1R_DATA2_Pos (16U)USART_SR_RXNE_Pos (5U)RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)RTC_TR_ST RTC_TR_ST_MskAPB2LPENRCAN_FM1R_FBM11_Pos (11U)EXTI_PR_PR15_Pos (15U)CAN_F9R1_FB29 CAN_F9R1_FB29_MskUSB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_MskGPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8__FLT32_MANT_DIG__ 24CAN_F2R1_FB24 CAN_F2R1_FB24_MskGPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0__GCC_IEC_559_COMPLEX 0TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)CoreDebug_DCRSR_REGSEL_Pos 0UCAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)CAN_FM1R_FBM8_Pos (8U)RTC_DR_DU RTC_DR_DU_MskADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)MPU_RASR_ENABLE_Pos 0UCAN_F1R1_FB6_Pos (6U)__CC_SUPPORTS___INLINE 1CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)TIM_SMCR_ETP_Pos (15U)CAN_F0R1_FB2 CAN_F0R1_FB2_MskSCB ((SCB_Type *) SCB_BASE )LL_SYSCFG_EXTI_PORTC (uint32_t)2RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_MskGPIO_AFRL_AFSEL6_1 0x02000000UEXTI_RTSR_TR17_Pos (17U)FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)USB_OTG_GINTSTS_SOF_Pos (3U)CAN_MCR_RFLM CAN_MCR_RFLM_MskGPIO_AFRH_AFSEL14_1 0x02000000UETH_MACA1HR_SA ETH_MACA1HR_SA_MskDCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RISCAN_F4R1_FB15_Pos (15U)LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)CAN_F2R1_FB22_Pos (22U)READ_REG(REG) ((REG))CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)LL_GPIO_OUTPUT_PUSHPULL (0x00000000U)SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_MskLL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOPUSB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_MskSPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)CAN_F11R2_FB16 CAN_F11R2_FB16_MskNVIC_GetActive __NVIC_GetActiveCAN_F4R1_FB5_Pos (5U)CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)__SIZE_TYPE__ unsigned intDAC_CR_TEN1_Pos (2U)FSMC_PMEM4_MEMWAIT4_Pos (8U)CAN_F4R1_FB10 CAN_F4R1_FB10_MskCAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)__FLT64_MAX_10_EXP__ 308CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_MskCAN_MSR_SAMP CAN_MSR_SAMP_MskCAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_MskI2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)CAN_F6R1_FB0_Pos (0U)DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_MskFSMC_BWTR1_DATAST_Pos (8U)CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)CAN_F7R2_FB17 CAN_F7R2_FB17_MskUSART_DR_DR_Pos (0U)RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)ETH_DMABMR_RDP ETH_DMABMR_RDP_MskCAN_F10R1_FB7 CAN_F10R1_FB7_Msk__lock_release(lock) __retarget_lock_release(lock)RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSELUSB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)bheapRCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)ETH_PTPTSCR_TSE_Pos (0U)GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)traceQUEUE_REGISTRY_ADD(xQueue,pcQueueName) _GLIBCXX_NORETURN __attribute__ ((__noreturn__))GPIO_AFRH_AFSEL8_2 0x00000004ULL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1TIM_CR2_CCDS TIM_CR2_CCDS_MskETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)status_outUSB_OTG_CHNUM_Pos (0U)__alloc_align(x) __attribute__((__alloc_align__(x)))DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)__DBL_MAX_10_EXP__ 308USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)SYSCFG_EXTICR2_EXTI5_PA 0x00000000UWCHAR_MINEXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)CAN_F10R2_FB11 CAN_F10R2_FB11_Msk__cpp_lib_three_way_comparison 201907LTIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U )DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)_GLIBCXX_HAVE_ICONV 1DAC_DHR8RD_DACC2DHR_Pos (8U)RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)CAN_F10R1_FB13 CAN_F10R1_FB13_MskCoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)CAN_F6R1_FB19_Pos (19U)offsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)CAN_F6R2_FB16_Pos (16U)FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)_GLIBCXX_NOEXCEPT noexceptCAN_F10R2_FB8_Pos (8U)RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)INT64_MAX __INT64_MAX__USB_OTG_DOEPMSK_BOIM_Pos (9U)__get_IPSRRCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)DMA_SxCR_TCIE DMA_SxCR_TCIE_MskGPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0DMA_LIFCR_CDMEIF1_Pos (8U)RTC_BKP_NUMBER 0x000000014UUSB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_MskUSB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)ETH_PTPTSSR_TSSIPV6FE_Pos (12U)__cpp_ref_qualifiers 200710LSDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)__static_initialization_and_destruction_0GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1USB_OTG_DOEPCTL_SNPM_Pos (20U)CAN_F9R1_FB20_Pos (20U)TIM_CCER_CC2NP TIM_CCER_CC2NP_MskFLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_MskCAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)EXTI_EMR_MR20 EXTI_EMR_MR20_MskARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)print_lineCAN_F12R1_FB27 CAN_F12R1_FB27_MskETH_MACMIIAR_CR_Div62_Pos (2U)DCMI_ESUR_FEU_Pos (24U)portHAS_STACK_OVERFLOW_CHECKING 0CAN_F8R1_FB29_Pos (29U)_PSTL_PRAGMA_DECLARE_SIMD _PSTL_PRAGMA(omp declare simd)FREERTOS_SYSTEM_CALL CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)__UINT64_C(c) c ## ULLUSB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)FSMC_SR4_IRS_Pos (0U)LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOPSCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)DMA_SxFCR_FTH DMA_SxFCR_FTH_MskGPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)ADC_CR1_JDISCEN_Pos (12U)FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)CAN_FA1R_FACT8 CAN_FA1R_FACT8_MskconfigEXPECTED_IDLE_TIME_BEFORE_SLEEP 2unsigned signedADC_CR1_AWDEN_Pos (23U)LL_DMA_STREAM_3 0x00000003U__CM_CMSIS_VERSION_SUB ( 1U)CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)ETH_MACSR_MMCTS ETH_MACSR_MMCTS_MskADC_JSQR_JSQ3_Pos (10U)CAN_F11R1_FB22_Pos (22U)FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)TIM_CR2_OIS3N TIM_CR2_OIS3N_MskUSART_CR1_RE USART_CR1_RE_MskADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)I2C_OAR2_ADD2 I2C_OAR2_ADD2_MskLL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)EXTI_SWIER_SWIER19_Pos (19U)CAN_F0R1_FB22_Pos (22U)RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_MskCAN_F8R2_FB11 CAN_F8R2_FB11_MskUSART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)AHB2ENRFSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)RTC_ALRMBR_DT RTC_ALRMBR_DT_MskRTC_ALRMAR_SU RTC_ALRMAR_SU_MskETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)CAN_F11R1_FB22 CAN_F11R1_FB22_MskCAN_F7R2_FB15_Pos (15U)DMA_HISR_TEIF7 DMA_HISR_TEIF7_MskCAN_F5R2_FB22_Pos (22U)GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)traceTASK_NOTIFY(uxIndexToNotify) CAN_F11R1_FB16_Pos (16U)ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)traceTASK_NOTIFY_WAIT(uxIndexToWait) EXTI_RTSR_TR3_Pos (3U)RCC_APB1LPENR_USART3LPEN_Pos (18U)DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_MskTIM_CCMR2_IC4F TIM_CCMR2_IC4F_MskRCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk__cpp_lib_make_reverse_iterator 201402LCAN_F2R2_FB5_Pos (5U)USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)CAN_F6R1_FB19 CAN_F6R1_FB19_MskRCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_MskSDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)__PRAGMA_REDEFINE_EXTNAME 1FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)CAN_FA1R_FACT6 CAN_FA1R_FACT6_MskLL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000UUSB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)__cpp_lib_sample 201603LEXTI_EMR_MR14 EXTI_EMR_MR14_MskRCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)__DEPRECATED 1TIM_BDTR_OSSR_Pos (11U)EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)__ARM_NEON__CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)UINT16_C_GLIBCXX_USE_CHAR8_T 1GPIO_AFRH_AFSEL10_0 0x00000100UARM_MPU_AP_FULL 3URTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)SPI_CR1_SSI_Pos (8U)CAN_TDH2R_DATA6_Pos (16U)ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)UINTMAX_C(c) __UINTMAX_C(c)CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)__GCC_DESTRUCTIVE_SIZE 64CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)EXTI_EMR_EM6 EXTI_EMR_MR6__cpp_lib_null_iterators 201304LSDIO_CMD_ENCMDCOMPL_Pos (12U)DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)_GLIBCXX98_USE_C99_STDIO 1CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)TIM_CCMR2_IC3PSC_Pos (2U)TPI_DEVTYPE_SubType_Pos 4UCAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)__ORDER_BIG_ENDIAN__ 4321CAN_F13R1_FB26_Pos (26U)ETH_MACA3HR_MBC_LBits23_16 0x04000000UUSB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)ETH_MACCR_RE ETH_MACCR_RE_MskITM_TPR_PRIVMASK_Pos 0UTIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)ETH_DMASR_TSTS ETH_DMASR_TSTS_MskTIM4 ((TIM_TypeDef *) TIM4_BASE)CAN_F13R1_FB11 CAN_F13R1_FB11_MskUSB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)MPU_CTRL_ENABLE_Msk (1UL )LL_GPIO_PIN_3 GPIO_BSRR_BS_3ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)FLASH_ACR_ICRST_Pos (11U)SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk_PSTL_PRAGMA_SIMD_EARLYEXIT USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_MskCAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)__LLFRACT_EPSILON__ 0x1P-63LLRDBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_MskFSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)ITM_TCR_SYNCENA_Pos 2UDCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_MskETH_MACDBGR_RFRCS_Pos (5U)ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msksync_withRCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)ETH_MACCR_WD ETH_MACCR_WD_MskI2C_SR1_BERR_Pos (8U)CAN_F9R2_FB2_Pos (2U)FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_MskSDIO_RESP1_CARDSTATUS1_Pos (0U)FSMC_PCR3_ECCPS_Pos (17U)CAN_F10R1_FB9_Pos (9U)TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)CAN_IER_BOFIE_Pos (10U)CAN_FA1R_FACT3 CAN_FA1R_FACT3_MskLL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)CAN_F7R2_FB24 CAN_F7R2_FB24_Msk__asserts_shared(...) __lock_annotate(assert_shared_lock(__VA_ARGS__))SYSCFG_EXTICR3_EXTI9_PH 0x00000070UCAN_F1R2_FB29 CAN_F1R2_FB29_MskSDIO_ICR_TXUNDERRC_Pos (4U)RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)EXTI_RTSR_TR17 EXTI_RTSR_TR17_MskSIGN_DATA_Port GPIODLL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)RCC_CR_HSIRDY RCC_CR_HSIRDY_MskGPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_MskpdFREERTOS_ERRNO_ENOTEMPTY 90DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_MskFSMC_SR2_IFEN FSMC_SR2_IFEN_MskUSB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk_GLIBCXX_HAVE_TANF 1ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_MskCAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)CAN_TDL0R_DATA0_Pos (0U)USART_CR1_IDLEIE USART_CR1_IDLEIE_MskRCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)UINTMAX_MAXDMA_HISR_TCIF4 DMA_HISR_TCIF4_MskCAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)portASSERT_IF_IN_ISR() ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQETH_MACFFR_HM ETH_MACFFR_HM_MskCAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)TPI_FIFO0_ETM2_Pos 16UtraceTASK_CREATE(pxNewTCB) ADC_CR2_CONT ADC_CR2_CONT_MskCAN_F8R2_FB5_Pos (5U)USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)__GCC_HAVE_DWARF2_CFI_ASM 1ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)guess_active_thread_nameFSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_MskCAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)RCC_CSR_PINRSTF_Pos (26U)__WCHAR_WIDTH__ 32EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)__result_use_check __attribute__((__warn_unused_result__))FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_MskCAN_F9R2_FB10 CAN_F9R2_FB10_MskDMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)EXTI_IMR_MR4 EXTI_IMR_MR4_MskCAN_F3R2_FB15 CAN_F3R2_FB15_MskEXTI_IMR_MR7_Pos (7U)CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)USB_OTG_GINTMSK_MMISM_Pos (1U)SYSCFG_EXTICR1_EXTI2_PF 0x00000500UADC_CR2_ADON_Pos (0U)RTC_ALRMBR_MSK2_Pos (15U)USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)_STL_RELOPS_H 1RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)CAN_F8R2_FB26 CAN_F8R2_FB26_Msk__cpp_nontype_template_args 201911LLL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4CAN_F0R2_FB12_Pos (12U)GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_MskCAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)DMA_LISR_FEIF0 DMA_LISR_FEIF0_MskCAN_F9R1_FB28 CAN_F9R1_FB28_MskSYSCFG_EXTICR1_EXTI0_PF 0x00000005UETH_MACA2LR_MACA2L_Pos (0U)GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)_GLIBCXX_NOEXCEPT_IF(...) noexcept(__VA_ARGS__)ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_MskCAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)USB_OTG_GINTSTS_HCINT_Pos (25U)CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)CAN_F2R1_FB6_Pos (6U)__GNUCLIKE_BUILTIN_VARARGS 1RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)CAN_F3R1_FB30 CAN_F3R1_FB30_Msk_REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk_REENT_EMERGENCY(_ptr) ((_ptr)->_emergency)EXTI_PR_PR2_Pos (2U)_ZN6tskmem6screenEFSMC_PCR4_PBKEN_Pos (2U)DCMI_ESCR_FEC_Pos (24U)FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)CAN_F2R2_FB22_Pos (22U)USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_MskCAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)CAN_F5R2_FB26 CAN_F5R2_FB26_MskETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_MskADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)CAN_FA1R_FACT11_Pos (11U)__ARM_FP16_FORMAT_ALTERNATIVEETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_MskCAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)RTC_ISR_ALRBF_Pos (9U)CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)CAN_F1R1_FB1 CAN_F1R1_FB1_MskCAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)__FLT32X_MIN_EXP__ (-1021)USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_MskCAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)__USFRACT_MAX__ 0XFFP-8UHRSYSCFG_EXTICR2_EXTI4_PG 0x00000006UFSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)CAN_F7R2_FB25 CAN_F7R2_FB25_MskCAN_TSR_TME2_Pos (28U)USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)CAN_F2R2_FB16_Pos (16U)EXTI_EMR_MR0_Pos (0U)DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)SDIO_STA_DCRCFAIL_Pos (1U)_PSTL_PRAGMA_SIMD_INCLUSIVE_SCAN(PRM) CAN_F6R1_FB26 CAN_F6R1_FB26_MskCAN_F7R1_FB10_Pos (10U)RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk_GCC_WRAP_STDINT_H CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)GPIO_AFRL_AFSEL1_1 0x00000020USYSCFG_EXTICR1_EXTI2_PG 0x00000600U__INT_LEAST16_MAX__ 0x7fffUSB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)CAN_F7R1_FB7 CAN_F7R1_FB7_MskFSMC_BCR3_MTYP_Pos (2U)CAN_F8R2_FB23 CAN_F8R2_FB23_MskEXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)ETH_MACMIIAR_CR ETH_MACMIIAR_CR_MskRCC_CFGR_PPRE1_DIV16 0x00001C00UUSART_CR1_PCE_Pos (10U)FSMC_PIO4_IOWAIT4_Pos (8U)CAN_F2R2_FB28 CAN_F2R2_FB28_MskDBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)FSMC_BWTR4_ACCMOD_Pos (28U)CAN_F9R1_FB3_Pos (3U)SPI_SR_OVR SPI_SR_OVR_Msk__GNUC_STDC_INLINE__ 1break_lineSYSCFG_EXTICR2_EXTI6_PA 0x00000000URCC_APB1LPENR_I2C1LPEN_Pos (21U)EXTI_EMR_MR19_Pos (19U)SCB_DFSR_BKPT_Pos 1UCAN_F5R1_FB27 CAN_F5R1_FB27_Msk__INT_FAST32_TYPE__ intxPSR_C_Pos 29U__lock_init_recursive(lock) __retarget_lock_init_recursive(&lock)__DBL_HAS_DENORM__ 1CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)LL_TIM_DIER_CC1IE TIM_DIER_CC1IECAN_F4R2_FB26_Pos (26U)FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_MskSPI_CR1_CRCNEXT_Pos (12U)USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)EXTI_IMR_IM8 EXTI_IMR_MR8USART_CR1_RWU_Pos (1U)RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)__WCHAR_TYPE__ unsigned intETH_MACFFR_HPF_Pos (10U)TIMx_OR_RMP_SHIFT 16UGPIO_OTYPER_OT_4 GPIO_OTYPER_OT4LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3)RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)CAN_F8R1_FB12 CAN_F8R1_FB12_MskSYSCFG_EXTICR3_EXTI8_PH 0x00000007UBKP6RCAN_F5R2_FB9 CAN_F5R2_FB9_Msk__cpp_lib_bit_cast 201806LCAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)CAN_F2R1_FB17 CAN_F2R1_FB17_Msk__ARM_ARCH_ISA_THUMBADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_MskCAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)USB_OTG_GRXSTSP_BCNT_Pos (4U)USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_MskUSB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_MskCoreDebug_DHCSR_S_RESET_ST_Pos 25UETH_DMABMR_PBL_4xPBL_128Beat 0x01002000UGPIO_ODR_ODR_3 GPIO_ODR_OD3TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)FSMC_SR3_IRS FSMC_SR3_IRS_MskLL_TIM_OCMODE_FROZEN 0x00000000USPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)_GLOBAL_REENT (&_impure_data)DMA_SxCR_TCIE_Pos (4U)traceTASK_PRIORITY_SET(pxTask,uxNewPriority) ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)CAN_TI1R_RTR_Pos (1U)CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)__cpp_attributes 200809LCAN_F2R1_FB27 CAN_F2R1_FB27_MskDMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)__cpp_lib_integer_comparison_functions 202002LGPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)__FDPIC____ptr_t void *RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)ETH_MMCRIMR_RGUFM_Pos (17U)CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk__ATTRIBUTE_IMPURE_PTR__ ETH_MACPMTCSR_MPE_Pos (1U)DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_MskCAN_F1R2_FB11 CAN_F1R2_FB11_MskGPIO_OSPEEDR_OSPEED3_1 0x00000080UFSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)traceTIMER_EXPIRED(pxTimer) __packed __attribute__((__packed__))PROJDEFS_H ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)SCB_CPUID_VARIANT_Pos 20UUSB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_MskCAN_F0R2_FB6_Pos (6U)ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)SPI_SR_CRCERR_Pos (4U)INT_FAST16_MAX __INT_FAST16_MAX__RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)SDIO_MASK_RXOVERRIE_Pos (5U)CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)GPIO_MODER_MODE10_0 0x00100000UCAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)TIM_CCMR2_OC4PE_Pos (11U)SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)PWR_CSR_EWUP_Pos (8U)__cpp_lib_is_final 201402LDCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)CAN_F0R2_FB15 CAN_F0R2_FB15_MskxSemaphoreCreateBinaryStatic(pxStaticSemaphore) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_MskDMA1_Stream4_IRQnGPIO_IDR_IDR_13 GPIO_IDR_ID13CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)EXTI_EMR_MR1 EXTI_EMR_MR1_MskRCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)MPU_CTRL_HFNMIENA_Pos 1UCAN_TDT2R_TIME CAN_TDT2R_TIME_Msk__long_double_t long doubleCAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)IWDG_SR_PVU IWDG_SR_PVU_MskFSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_MskFSMC_BCR3_WAITPOL_Pos (9U)FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_MskEXTI_IMR_MR10_Pos (10U)LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)RCC_APB1LPENR_CAN1LPEN_Pos (25U)CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRCUSB_OTG_DOEPCTL_STALL_Pos (21U)USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_MskCAN_F7R1_FB25 CAN_F7R1_FB25_MskRCC_CR_HSEBYP_Pos (18U)ETH_MACCR_ROD ETH_MACCR_ROD_MskUSART_CR1_RXNEIE USART_CR1_RXNEIE_MskETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_MskCAN_F5R1_FB0 CAN_F5R1_FB0_MskWWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)RCC_CR_HSERDY RCC_CR_HSERDY_Msk__ULACCUM_IBIT__ 32ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_MskEXTI_RTSR_TR12 EXTI_RTSR_TR12_MskADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_MskFSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_MskFSMC_SR4_IREN_Pos (3U)RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)FSMC_PCR4_PWAITEN_Pos (1U)RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)_GLIBCXX_HAS_BUILTINCAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)FSMC_BCR2_EXTMOD_Pos (14U)CAN_F7R2_FB3_Pos (3U)SDIO_ICR_DCRCFAILC_Pos (1U)CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk_GLIBCXX_PSEUDO_VISIBILITY(V) SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)EXTI_FTSR_TR22 EXTI_FTSR_TR22_MskCAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_MskRCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)_PSTL_PRAGMA_MESSAGE_IMPL(x) _PSTL_PRAGMA(message(_PSTL_STRING_CONCAT(_PSTL_PRAGMA_LOCATION, x)))LL_GPIO_PIN_4 GPIO_BSRR_BS_4ADC_JOFR3_JOFFSET3_Pos (0U)ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)__FLT32X_MIN_10_EXP__ (-307)__ARM_EABI__ 1RCC_CR_PLLI2SRDY_Pos (27U)CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)DMA_SxM1AR_M1A DMA_SxM1AR_M1A_MskEXTI_RTSR_TR11 EXTI_RTSR_TR11_MskCAN_F12R1_FB19 CAN_F12R1_FB19_MskDMA_HISR_TCIF6_Pos (21U)TIM_SMCR_MSM_Pos (7U)SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)EXTI_RTSR_TR12_Pos (12U)CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_MskDMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk__WFE() __ASM volatile ("wfe")CAN_F3R2_FB2 CAN_F3R2_FB2_MskSDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)CAN_F9R1_FB11 CAN_F9R1_FB11_MsklistTEST_LIST_ITEM_INTEGRITY(pxItem) CAN_F3R1_FB16 CAN_F3R1_FB16_MskDMA2_Stream6_IRQnCAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)DAC_CR_TSEL1 DAC_CR_TSEL1_MskUSB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK)CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)EXTI_IMR_MR16 EXTI_IMR_MR16_MskSYSCFG_EXTICR4_EXTI13_PG 0x00000060UUSB_OTG_DOEPINT_EPDISD_Pos (1U)LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14ENETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)SPI_CR2_TXEIE_Pos (7U)__INT_LEAST32_MAX__ 0x7fffffffLFSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)_GLIBCXX_HAVE_VFWSCANF 1LL_DMA_SetChannelSelectionTIM_CCER_CC4E TIM_CCER_CC4E_MskTIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)RCC_APB2ENR_SYSCFGEN_Pos (14U)_FUNCTEXCEPT_H 1FSMC_PCR2_TAR_Pos (13U)USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)CAN_RDL0R_DATA0_Pos (0U)__cpp_decltype 200707LDAC_CR_MAMP1 DAC_CR_MAMP1_MskUSB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)DWT_FUNCTION_CYCMATCH_Pos 7UCAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)___int_size_t_h CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)RTC_TSTR_MNT_Pos (12U)CAN_F0R2_FB7_Pos (7U)CAN_F1R2_FB30 CAN_F1R2_FB30_MskRCC_AHB1ENR_OTGHSEN_Pos (29U)CAN_F2R1_FB11_Pos (11U)TIM_CCER_CC4E_Pos (12U)CAN_F8R2_FB30 CAN_F8R2_FB30_MskTIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk__GCC_ATOMIC_POINTER_LOCK_FREE 2CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)CAN_F1R2_FB26_Pos (26U)EXTI_PR_PR21_Pos (21U)CAN_F11R1_FB14 CAN_F11R1_FB14_MskGPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)__glibcxx_requires_cond(_Cond,_Msg) SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_MskETH_MACFFR_PCF_Pos (6U)DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)__cpp_lib_integral_constant_callable 201304LMPU_RASR_AP_Pos 24UTIM_CCMR2_CC3S_Pos (0U)SPI_CR2_RXNEIE SPI_CR2_RXNEIE_MskDAC_SWTRIGR_SWTRIG1_Pos (0U)GPIO_MODER_MODER7_Pos (14U)FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)TIM_GET_CHANNEL_INDEX(__CHANNEL__) (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U : ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U : ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_MskGPIO_BSRR_BS_0 GPIO_BSRR_BS0CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)DCMI_ESCR_FSC_Pos (0U)RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)RCC_CFGR_I2SSRC_Pos (23U)USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk__ARM_32BIT_STATE 1RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)pdFREERTOS_ERRNO_EROFS 30ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)_GLIBCXX_STD_A stdTIM_CNT_CNT_Pos (0U)CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)RCC_APB1RSTR_TIM2RST_Pos (0U)IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))CAN_F11R2_FB21 CAN_F11R2_FB21_MskRCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)SYSCFG_EXTICR4_EXTI13_PE 0x00000040USDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)USB_OTG_DOEPMSK_AHBERRM_Pos (2U)CAN_F4R2_FB21 CAN_F4R2_FB21_MskUSB_OTG_GINTSTS_USBSUSP_Pos (11U)portSHORT shortGPIO_BSRR_BS_4 GPIO_BSRR_BS4LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_MskETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)__DBL_DECIMAL_DIG__ 17ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)CAN_FFA1R_FFA13_Pos (13U)traceEVENT_GROUP_CREATE_FAILED() USB_OTG_DCTL_CGONAK_Pos (10U)USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_MskETH_MACDBGR_TFF ETH_MACDBGR_TFF_MskRTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_MskCAN_RDT0R_FMI CAN_RDT0R_FMI_MskUSB_OTG_FRMNUM_Pos (21U)RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_MskFSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)TPI_FIFO1_ITM0_Msk (0xFFUL )ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_MskCAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)CAN_F2R1_FB29 CAN_F2R1_FB29_MskCAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)SYSCFG_EXTICR3_EXTI9_PF 0x00000050UETH_DMASR_TJTS ETH_DMASR_TJTS_Msk__USED __attribute__((used))__ARM_FEATURE_MATMUL_INT8CAN_F6R1_FB31_Pos (31U)dma_finished_ANSIDECL_H_ GPIO_BSRR_BS_8 GPIO_BSRR_BS8_CPP_TYPE_TRAITS_H 1_NEWLIB_VERSION "4.4.0"LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2)ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)SET_BIT(REG,BIT) ((REG) |= (BIT))__ARM_NEONGPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1LL_GPIO_PIN_11 GPIO_BSRR_BS_11EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_MskCAN_FS1R_FSC19_Pos (19U)CAN_F12R2_FB0 CAN_F12R2_FB0_MskRCC_CIR_PLLRDYC_Pos (20U)DCMI_CR_ESS_Pos (4U)CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_MskRTC_ISR_INITS RTC_ISR_INITS_MskSCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_MskCAN_F13R2_FB10 CAN_F13R2_FB10_MskCAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)PWR_CR_DBP PWR_CR_DBP_MskCAN_F11R1_FB0_Pos (0U)RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)TIM_CR1_URS TIM_CR1_URS_MskGPIO_OSPEEDR_OSPEED2_1 0x00000020U__INTMAX_MAX__ 0x7fffffffffffffffLL__DBL_MANT_DIG__ 53ETH_DMABMR_RDP_8Beat 0x00100000UCAN_F6R1_FB25_Pos (25U)ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U__UINT32_C(c) c ## ULCAN_FFA1R_FFA4 CAN_FFA1R_FFA4_MskCAN_FS1R_FSC5_Pos (5U)ETH_PTPTSCR_TSARU_Pos (5U)CAN_F5R2_FB16 CAN_F5R2_FB16_MskportNVIC_PENDSVSET_BIT ( 1UL << 28UL )CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)xTaskNotifyAndQuery(xTaskToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_MskLL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)traceQUEUE_RECEIVE_FROM_ISR(pxQueue) FLASH ((FLASH_TypeDef *) FLASH_R_BASE)_ZN4gpio3PinILm1073873920ELm6EEaSERKbADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)GPIO_OTYPER_OT12 0x00001000UCAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)USB_OTG_HCINT_FRMOR_Pos (9U)ETH_IRQnEXTI_PR_PR12 EXTI_PR_PR12_MskITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)SPI_RXCRCR_RXCRC_Pos (0U)CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)ucDummy19_REENT_ERRNO(_ptr) ((_ptr)->_errno)CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)DMA_HIFCR_CDMEIF5_Pos (8U)CAN_F5R2_FB11_Pos (11U)RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_MskLL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1)printedADC_CCR_DDS ADC_CCR_DDS_MskCAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk__glibcxx_digits10(_Tp) __glibcxx_floating(_Tp, __FLT_DIG__, __DBL_DIG__, __LDBL_DIG__)ADC_JDR3_JDATA_Pos (0U)FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)listLIST_ITEM_CONTAINER(pxListItem) ( ( pxListItem )->pxContainer )msign_panicTIM_BDTR_BKE TIM_BDTR_BKE_MsktraceTASK_DELAY() DBGMCU_IDCODE_REV_ID_Pos (16U)SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)CAN_F0R2_FB27_Pos (27U)GPIO_PUPDR_PUPD5 0x00000C00UCAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)ETH_MACHTHR_HTH_Pos (0U)_REENT_INIT_PTR_ZEROED(var) { (var)->_stdin = &__sf[0]; (var)->_stdout = &__sf[1]; (var)->_stderr = &__sf[2]; (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; }PRINTERUSB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_MskSDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_MskCAN_RF0R_FMP0 CAN_RF0R_FMP0_MskMPU_RNR_REGION_Msk (0xFFUL )ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)traceBLOCKING_ON_QUEUE_RECEIVE(pxQueue) ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)I2C_CR1_POS I2C_CR1_POS_MskFSMC_BCR4_WREN FSMC_BCR4_WREN_MskCAN_F3R1_FB23 CAN_F3R1_FB23_MskADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)CAN_F7R2_FB21_Pos (21U)TIM_CCMR1_IC2PSC_Pos (10U)EXTI_PR_PR5 EXTI_PR_PR5_MskCAN_TDT2R_TGT_Pos (8U)ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)DCMI_SR_VSYNC DCMI_SR_VSYNC_MskUSB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_MskUSB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)CAN_F5R2_FB20 CAN_F5R2_FB20_MskRCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_MskADC_SMPR2_SMP4 ADC_SMPR2_SMP4_MskCAN_FA1R_FACT10 CAN_FA1R_FACT10_MskUSB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_MskSYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_MskLL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)__STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24) |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16) |(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 ) |(__STM32F2xx_CMSIS_VERSION))ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)NVIC_SetPriority __NVIC_SetPriorityCAN_F1R1_FB24_Pos (24U)USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)CAN_F7R2_FB13 CAN_F7R2_FB13_MskSCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_MskEXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_MskCAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)UINT_FAST64_MAX __UINT_FAST64_MAX__ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)RCC_APB2ENR_ADC2EN_Pos (9U)EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_MskUSB_OTG_GINTSTS_EOPF_Pos (15U)SCB_VTOR_TBLOFF_Pos 7UconfigTICK_RATE_HZ ((TickType_t)1000)CAN_F9R2_FB31_Pos (31U)_ZNK3srv8Servicer11PendRequest11TimeRequestcvbEvADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)__THUMB_INTERWORK__ 1CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_MskDMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)RCC_APB1ENR_DACEN_Pos (29U)__lock_release_recursive(lock) __retarget_lock_release_recursive(lock)CAN_F8R2_FB16 CAN_F8R2_FB16_MskETH_DMATPDR_TPD ETH_DMATPDR_TPD_MskCAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)DWT_FUNCTION_DATAVSIZE_Pos 10U_PSTL_CPP14_INTEGER_SEQUENCE_PRESENT (_MSC_VER >= 1900 || __cplusplus >= 201402L)FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_MskDMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)ETH_DMASR_TPS_Suspended_Pos (21U)RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)_WANT_REGISTER_FINI 1CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0_BSD_SIZE_T_DEFINED_ CAN_F7R1_FB31_Pos (31U)SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_MskEXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)CAN_F9R2_FB25_Pos (25U)_HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1CAN_F4R2_FB13 CAN_F4R2_FB13_MskCAN_F1R1_FB15_Pos (15U)EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1EUINT_FAST8_MAX __UINT_FAST8_MAX__CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)FSMC_BCR1_WAITEN_Pos (13U)ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_MskRCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)I2C_OAR1_ADD0_Pos (0U)FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)ADC_CDR_DATA2 ADC_CDR_DATA2_MskUSB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_MskMSN_MINDRAW_H CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)DAC_CR_WAVE2_Pos (22U)RNG_SR_CEIS RNG_SR_CEIS_MskCAN_TDT2R_TGT CAN_TDT2R_TGT_MskCAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)ETH_MACCR_LM_Pos (12U)USART_CR3_CTSE_Pos (9U)CAN_F8R1_FB31 CAN_F8R1_FB31_MskRCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_MskFSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_MskCAN_F8R2_FB3_Pos (3U)RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)CAN_FM1R_FBM7_Pos (7U)PWR_CR_PLS_LEV6 0x000000C0UCAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)pdFREERTOS_ERRNO_EBADE 50ICPRDMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)RCC_AHB2ENR_RNGEN_Pos (6U)FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )SysTick_CTRL_ENABLE_Pos 0UPriorityGroupCAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)ETH_MACDBGR_MTFCS_WAITING_Pos (17U)ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)CAN_F3R1_FB25_Pos (25U)__glibcxx_digits10FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)__FLT32_DECIMAL_DIG__ 9MPU_TYPE_IREGION_Pos 16UUSB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)SDIO_CLKCR_WIDBUS_Pos (11U)FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)ITM_IRR_ATREADYM_Pos 0UDAC_DHR8R2_DACC2DHR_Pos (0U)USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_MskUSART1_BASE (APB2PERIPH_BASE + 0x1000UL)USART_CR1_RXNEIE_Pos (5U)CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)__UINT_LEAST8_TYPE__ unsigned charFSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)EXTI_EMR_MR9_Pos (9U)DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_MskFSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_MskRTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)CAN_F3R1_FB19_Pos (19U)RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1CAN_F13R1_FB8_Pos (8U)GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1CAN_F4R1_FB22 CAN_F4R1_FB22_MskLL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)__GNUCLIKE_CTOR_SECTION_HANDLING 1RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)__glibcxx_requires_partitioned_upper(_First,_Last,_Value) CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)CAN_FA1R_FACT_Pos (0U)USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_MskRTC_ISR_INITS_Pos (4U)CAN_F7R2_FB29 CAN_F7R2_FB29_MskDMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)LL_GPIO_SPEED_FREQ_LOW (0x00000000U)SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)RCC_CIR_LSERDYC RCC_CIR_LSERDYC_MskSCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)DCMI ((DCMI_TypeDef *) DCMI_BASE)USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_MskGPIO_IDR_IDR_11 GPIO_IDR_ID11RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk__LDBL_HAS_INFINITY__ 1xTaskNotifyIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)CAN_FM1R_FBM18 CAN_FM1R_FBM18_MskUSART_CR3_ONEBIT_Pos (11U)CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_MskSPI_TXCRCR_TXCRC_Pos (0U)FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)CAN_F5R1_FB29_Pos (29U)ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000ULL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)USB_OTG_HPRT_POCA_Pos (4U)GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0__SIZEOF_LONG_DOUBLE__ 8SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_MskDMA_SxCR_PBURST_Pos (21U)SYSCFG_EXTICR1_EXTI0_PI 0x00000008UFSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)CAN_F7R1_FB18 CAN_F7R1_FB18_MskDMA_SxPAR_PA_Pos (0U)RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_MskUSB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk__volatile volatileFSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_MskCAN_F0R1_FB13 CAN_F0R1_FB13_MskETH_MACFCR_PLT_Minus256_Pos (4U)RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)CAN_F4R2_FB21_Pos (21U)_GXX_NULLPTR_T ICSRqueueOVERWRITE ( ( BaseType_t ) 2 )INCLUDE_eTaskGetState 0MPU_RASR_C_Pos 17UUART5_BASE (APB1PERIPH_BASE + 0x5000UL)SDIO_STA_TXACT SDIO_STA_TXACT_MskCAN_MCR_SLEEP_Pos (1U)ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)12SysTick_TypeFSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)CoreDebug_DEMCR_VC_CHKERR_Pos 6URTC_CR_TSE RTC_CR_TSE_MskCAN_F9R2_FB9 CAN_F9R2_FB9_MskLL_TIM_DIER_CC2IE TIM_DIER_CC2IECAN_ESR_LEC CAN_ESR_LEC_MskCAN_MCR_AWUM CAN_MCR_AWUM_MskUSB_OTG_DIEPINT_TXFE_Pos (7U)RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)EXTI_FTSR_TR14 EXTI_FTSR_TR14_MskportCHAR char__DQ_IBIT__ 0CAN_MSR_SLAKI CAN_MSR_SLAKI_MskCAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)CAN_F4R2_FB15_Pos (15U)FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)tskmemFLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)_scdataCAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)GPIO_LCKR_LCK14_Pos (14U)GPIO_LCKR_LCK3_Pos (3U)RCC_CFGR_PPRE2_DIV8 0x0000C000UDMA_HISR_HTIF5_Pos (10U)FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)ETH_MACA1LR_MACA1L_Pos (0U)IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))CAN_F12R2_FB23 CAN_F12R2_FB23_MskCAN_F5R1_FB5_Pos (5U)xSemaphoreTakeRecursive(xMutex,xBlockTime) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)EXTI_RTSR_TR0 EXTI_RTSR_TR0_MskTIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)_RANGES_ALGOBASE_H 1DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)DCMI_CR_CRE DCMI_CR_CRE_MskCAN_RI0R_IDE_Pos (2U)RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk__CC_SUPPORTS_VARADIC_XXX 1_ZN5crash6MatrixC4Ev__POSIX_VISIBLE 200809USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)configENABLE_BACKWARD_COMPATIBILITY 1DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)ETH_MACMIIDR_MD ETH_MACMIIDR_MD_MskCAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)_GLIBCXX17_DEPRECATED [[__deprecated__]]CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)RCC_APB1RSTR_USART2RST_Pos (17U)USB_OTG_DIEPINT_EPDISD_Pos (1U)I2C_CR1_ENPEC_Pos (5U)I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)USART_SR_TXE_Pos (7U)ITM_TCR_BUSY_Pos 23UCAN_F12R1_FB0_Pos (0U)FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)configUSE_TICKLESS_IDLE 0CAN_F6R2_FB25_Pos (25U)CAN_F2R1_FB9 CAN_F2R1_FB9_MskCAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)CAN_F8R1_FB4_Pos (4U)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)__cpp_constinit 201907LDMA_HIFCR_CHTIF7_Pos (26U)MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)__FLT_IS_IEC_60559__ 1CPUIDRTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)RTC_TR_MNT_Pos (12U)GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_MskDBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)__cust__LDBL_MIN__ 2.2250738585072014e-308LFSMC_BWTR3_BUSTURN_Pos (16U)result_writeLL_TIM_CHANNEL_CH2N TIM_CCER_CC2NECAN_F9R2_FB15_Pos (15U)__glibcxx_requires_can_increment_range(_First1,_Last1,_First2) RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_MskDMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)__INT16_MAX__ 0x7fffCAN_F6R2_FB19_Pos (19U)SDIO_MASK_DATAENDIE_Pos (8U)CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_MskCAN_F11R2_FB8_Pos (8U)ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)EXTI_EMR_MR16_Pos (16U)USART_SR_FE_Pos (1U)CAN_F5R2_FB27_Pos (27U)I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)AHB3RSTRCAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)USB_OTG_HOST_CHANNEL_SIZE 0x20ULETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_MskUSB_OTG_HCINTMSK_CHHM_Pos (1U)CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)CAN_F6R2_FB9 CAN_F6R2_FB9_MskDMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)__SACCUM_IBIT__ 8USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)__UDQ_FBIT__ 64LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3)FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)14SYSCFG_TypeDefconfigUSE_NEWLIB_REENTRANT 0PriorityGroupTmpGPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)CONTROL_nPRIV_Pos 0ULL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1RTC_BKP16R RTC_BKP16R_MskCAN_FM1R_FBM0_Pos (0U)CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)RCC_CFGR_PPRE2_DIV4 0x0000A000UCAN_F4R2_FB14 CAN_F4R2_FB14_MskCAN_F11R2_FB13 CAN_F11R2_FB13_MskSDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_MskLL_TIM_SR_CC1IF TIM_SR_CC1IFCAN_F12R2_FB1_Pos (1U)RTC_ISR_ALRBWF RTC_ISR_ALRBWF_MskRCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)GPIO_BSRR_BR_15 GPIO_BSRR_BR15BDTRCAN_F9R1_FB0 CAN_F9R1_FB0_MskTIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)USB_OTG_GCCFG_I2CPADEN_Pos (17U)CAN_F8R2_FB0 CAN_F8R2_FB0_MskSYSCFG_EXTICR4_EXTI12_PA 0x00000000UDMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2TPI_FFSR_TCPresent_Pos 2UTPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)FSMC_BTR1_ADDSET_Pos (0U)CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)CAN_F0R1_FB19_Pos (19U)CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)CAN_F8R1_FB17 CAN_F8R1_FB17_MskUART4_BASE (APB1PERIPH_BASE + 0x4C00UL)RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk__cpp_lib_has_unique_object_representations 201606LIWDG_SR_RVU_Pos (1U)TIM4_IRQn_PSTL_PRAGMA_SIMD_SCAN(PRM) FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_MskSYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_MskPLLI2SCFGRUSB_OTG_GINTSTS_SRQINT_Pos (30U)_ZN6tskmem10TaskHolderILj512EE6createEPFvPvEPKcS2_mDMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)RCC_CFGR_HPRE_DIV128 0x000000D0UOTG_HS_EP1_OUT_IRQnEXTI_IMR_IM11 EXTI_IMR_MR11CAN_FA1R_FACT14_Pos (14U)CAN_F11R2_FB22_Pos (22U)ADC_CSR_JSTRT3_Pos (19U)_GLIBCXX_HAVE_VSWSCANF 1FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_MskETH_MMCTGFCR_TGFC_Pos (0U)CAN_F8R1_FB2 CAN_F8R1_FB2_MskFSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)PWR_BASE (APB1PERIPH_BASE + 0x7000UL)GPIO_AFRL_AFSEL2_2 0x00000400UCAN_F13R1_FB29 CAN_F13R1_FB29_MskINT_FAST16_MIN (-INT_FAST16_MAX - 1)SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)ARM_MPU_CACHEP_WT_NWA 2UMPU_BASE (SCS_BASE + 0x0D90UL)CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)EXTI_IMR_MR8_Pos (8U)LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOSFSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)NVIC_SRV_TX_IRQ_HANDLER DMA2_Stream7_IRQHandlerCAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)FSMC_PMEM2_MEMWAIT2_Pos (8U)CAN_F0R2_FB31 CAN_F0R2_FB31_MskCAN_F2R1_FB29_Pos (29U)ETH_DMASR_ETS_Pos (10U)_GLIBCXX_DOXYGEN_ONLY(X) ADC_CR2_EOCS_Pos (10U)FSMC_SR4_ILEN_Pos (4U)RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)EXTI_IMR_IM15 EXTI_IMR_MR15CAN_F11R2_FB16_Pos (16U)CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)__ARM_FEATURE_BTI_DEFAULTUSART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)RTC_ISR_INIT_Pos (7U)__STM32F2xx_CMSIS_VERSION_SUB1 (0x02U)RTC_TSTR_HU_Pos (16U)CALIBCAN_F6R2_FB4 CAN_F6R2_FB4_MskCAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)SDIO_CMD_WAITINT_Pos (8U)INCLUDE_uxTaskPriorityGet 1SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_MskCAN_TDT1R_TIME CAN_TDT1R_TIME_MskAPSR_C_Pos 29UDCMI_CR_CAPTURE_Pos (0U)RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_MskUSB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_MskDCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_MskRCC_CFGR_HPRE RCC_CFGR_HPRE_MskETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRCAN_F12R1_FB24 CAN_F12R1_FB24_MskFSMC_SR2_ILS FSMC_SR2_ILS_MskCAN_F0R1_FB20 CAN_F0R1_FB20_MskCAN_F12R1_FB30_Pos (30U)__DEFINED_ptrdiff_t CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)traceTASK_DELAY_UNTIL(x) ___int16_t_defined 1ETH_DMABMR_FB_Pos (16U)CAN_F5R1_FB3_Pos (3U)CAN_F9R2_FB22 CAN_F9R2_FB22_MskUSB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)RCC_APB2RSTR_TIM11RST_Pos (18U)CoreDebug_DHCSR_S_SLEEP_Pos 18UCAN_F10R2_FB8 CAN_F10R2_FB8_MskEXTI_PR_PR10_Pos (10U)USB_OTG_BCNT USB_OTG_BCNT_MskCAN_F13R2_FB26_Pos (26U)GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)ADC_SR_JEOC ADC_SR_JEOC_MskCAN_F12R2_FB4 CAN_F12R2_FB4_MskSYSCFG_EXTICR2_EXTI4_Pos (0U)ETH_MACMIIAR_MW ETH_MACMIIAR_MW_MskvQueueUnregisterQueue(xQueue) USB_OTG_HPRT_PLSTS_Pos (10U)12GPIO_TypeDefSYSCFG_PMC_MII_RMII_SEL_Pos (23U)CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)RCC_APB1ENR_TIM14EN_Pos (8U)TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)I2C1_EV_IRQnGPIO_IDR_IDR_4 GPIO_IDR_ID4CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)GPIO_ODR_ODR_14 GPIO_ODR_OD14TIM_DIER_UIE TIM_DIER_UIE_MskCAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)LL_TIM_ETR_PRESCALER_DIV1 0x00000000UUSB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)_GLIBCXX11_USE_C99_STDLIB 1ETH_DMAMFBOCR_OMFC_Pos (16U)CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)CAN_F4R1_FB10_Pos (10U)xSemaphoreGive(xSemaphore) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )ETH_DMAOMR_FTF_Pos (20U)CAN_F11R1_FB0 CAN_F11R1_FB0_MskUSB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_MskCAN_F11R1_FB9_Pos (9U)CAN_F9R2_FB14 CAN_F9R2_FB14_MskCAN_F5R2_FB13 CAN_F5R2_FB13_MskDMA_LISR_TCIF2 DMA_LISR_TCIF2_MskCAN_F0R2_FB24_Pos (24U)SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)CAN_F9R2_FB5_Pos (5U)__UTQ_IBIT__ 0CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)SCB_ICSR_VECTACTIVE_Pos 0U__SIZE_T__ portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )ADC_LTR_LT ADC_LTR_LT_MskRCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_MskGPIO_OSPEEDR_OSPEED5 0x00000C00UTIM_CCER_CC1E TIM_CCER_CC1E_MskSDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)CAN_F3R1_FB4 CAN_F3R1_FB4_MskLL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOPSYSCFG_EXTICR1_EXTI1_PE 0x00000040UIWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1CAN_F3R2_FB19_Pos (19U)USB_OTG_FS_MAX_OUT_ENDPOINTS 4UFSMC_BWTR4_DATAST_2 (0x04UL << FSMC_BWTR4_DATAST_Pos)__ARM_FEATURE_QRDMXRCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)strlenCAN_F6R1_FB20_Pos (20U)FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)ADC_SMPR1_SMP11_Pos (3U)ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)SDIO_STA_TXDAVL SDIO_STA_TXDAVL_MskETH_MACVLANTR_VLANTC_Pos (16U)RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)SYSCFG_EXTICR1_EXTI3_PH 0x00007000UTIM8_BASE (APB2PERIPH_BASE + 0x0400UL)CAN_F5R2_FB20_Pos (20U)CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)CAN_F1R1_FB21_Pos (21U)FSMC_PCR4_TCLR_Pos (9U)__glibcxx_class_requires2(_a,_b,_c) RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)CAN_F6R2_FB31_Pos (31U)FSMC_BWTR2_ADDSET_Pos (0U)TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)CAN_F13R2_FB30 CAN_F13R2_FB30_MskETH_DMASR_EBS ETH_DMASR_EBS_Msk__cpp_nested_namespace_definitions 201411LGPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)ADC_SQR2_SQ11_Pos (20U)CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)ESP_USART_TX LL_GPIO_PIN_14CAN_F1R2_FB6 CAN_F1R2_FB6_MskUSB_OTG_GRSTCTL_TXFNUM_Pos (6U)FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)CAN_F6R1_FB14_Pos (14U)FSMC_BCR1_MBKEN_Pos (0U)EXTI_FTSR_TR17_Pos (17U)FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_MskSPI_SR_CRCERR SPI_SR_CRCERR_MskCAN_F5R2_FB29_Pos (29U)CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)ETH_DMAOMR_RTC_Pos (3U)SYSCFG_EXTICR1_EXTI3_PE 0x00004000UCAN_TDL0R_DATA1_Pos (8U)ADC_CSR_JEOC3 ADC_CSR_JEOC3_MskRTC_BKP9R_Pos (0U)INT_FAST64_MIN__cpp_initializer_lists 200806LTIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)RCC_SSCGR_SPREADSEL_Pos (30U)IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || ((INSTANCE) == CAN2))SYSCFG_CMPCR_READY_Pos (8U)__LACCUM_EPSILON__ 0x1P-31LKCAN_FS1R_FSC25_Pos (25U)RTC_TSTR_MNU_Pos (8U)FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)CAN_MSR_TXM_Pos (8U)CAN_F3R1_FB6_Pos (6U)LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)TIM_EGR_COMG_Pos (5U)CAN_F8R1_FB24 CAN_F8R1_FB24_MskEXTI_RTSR_TR14 EXTI_RTSR_TR14_MskSHIFT_TAB_ICxxCAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)CAN_FA1R_FACT3_Pos (3U)FLASH_CR_LOCK FLASH_CR_LOCK_Msk__cpp_template_template_args 201611LCAN_F8R1_FB24_Pos (24U)USART_SR_TC_Pos (6U)ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_MskRTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)EXTI_SWIER_SWIER20_Pos (20U)LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3ENRCC_AHB1ENR_BKPSRAMEN_Pos (18U)CAN_F4R2_FB26 CAN_F4R2_FB26_MskDWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)SYSCFG_EXTICR2_EXTI7_PG 0x00006000UTIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_MskCAN_F2R2_FB27 CAN_F2R2_FB27_MskTIM_BDTR_BKP TIM_BDTR_BKP_MskCAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)CAN_F10R1_FB1_Pos (1U)DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)CAN_F5R1_FB28 CAN_F5R1_FB28_MskDMA_SxCR_PINC DMA_SxCR_PINC_MskCAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)ETH_DMASR_RPS_Suspended_Pos (19U)CAN_F6R1_FB5_Pos (5U)CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_MskUSB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_MskGPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)CAN_TI2R_IDE CAN_TI2R_IDE_Msk_ZN6tskmem6dbgtimECoreDebug_DHCSR_S_HALT_Pos 17UCAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_MskUSB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)I2C_CR1_POS_Pos (11U)EXTI_FTSR_TR9 EXTI_FTSR_TR9_MskSYSCFG_EXTICR2_EXTI7_PD 0x00003000ULL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1ENETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_MskFSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)NVIC_SRV_TX_CLRF LL_DMA_ClearFlag_TC7LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)SYSCFG_EXTICR4_EXTI13_PC 0x00000020UADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)CAN_F7R2_FB10_Pos (10U)CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)_PSTL_USE_NONTEMPORAL_STORES_IF_ALLOWED USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1CAN_F10R2_FB17 CAN_F10R2_FB17_MskSDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)FSMC_BTR2_BUSTURN_Pos (16U)CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)CAN_F0R2_FB17 CAN_F0R2_FB17_MskCAN_F10R2_FB26_Pos (26U)ETH_MACCR_DM ETH_MACCR_DM_MskUSB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk__cpp_guaranteed_copy_elision 201606LSYSCFG_EXTICR3_EXTI13_PH 0x00000070UEXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)ETH_MACFFR_SAF_Pos (9U)GPIO_OTYPER_OT7 0x00000080URTC ((RTC_TypeDef *) RTC_BASE)I2C_OAR1_ADD9_Pos (9U)_SIZE_T_DECLARED SCB_ICSR_ISRPENDING_Pos 22USYSCFG_EXTICR3_EXTI9_PD 0x00000030UUSB_OTG_DIEPINT_NAK_Pos (13U)__ACCUM_EPSILON__ 0x1P-15K__SHRT_MAX__ 0x7fffEXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)__builtin_align_up(x,align) ((__typeof__(x))(((__uintptr_t)(x)+((align)-1))&(~((align)-1))))TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)IWDG_RLR_RL IWDG_RLR_RL_MskETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_MskCAN_F12R2_FB8_Pos (8U)BKP0RCAN_F10R2_FB26 CAN_F10R2_FB26_MskCAN_F9R2_FB20_Pos (20U)RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_MskRCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_MskRTC_ISR_TSOVF_Pos (12U)RCC_CIR_CSSF RCC_CIR_CSSF_Msk__LFRACT_IBIT__ 0CAN_F4R1_FB13 CAN_F4R1_FB13_MskCAN_F13R1_FB21_Pos (21U)__INT_FAST16_TYPE__ intCAN_FFA1R_FFA24 CAN_FFA1R_FFA24_MskCAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)__cpp_lib_bool_constant 201505LUSB_OTG_HCTSIZ_PKTCNT_Pos (19U)I2C_CCR_FS I2C_CCR_FS_MskCAN_F1R2_FB29_Pos (29U)USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_MskLL_TIM_DisableCounterIS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8))TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)EXTI_FTSR_TR8_Pos (8U)ETH_PTPTSHUR_TSUS_Pos (0U)SCB_AIRCR_VECTRESET_Pos 0UCAN_F0R2_FB12 CAN_F0R2_FB12_MskCAN_F9R2_FB14_Pos (14U)LL_SYSCFG_EXTI_PORTD (uint32_t)3BKP1RCAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_MskUSB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)GPIO_BSRR_BS14 0x00004000UCAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_MskETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_MskADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)CAN_F8R2_FB15_Pos (15U)I2C_CR2_FREQ_Pos (0U)FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_MskFSMC_BTR1_DATAST_Pos (8U)TIM_CR2_OIS4_Pos (14U)ADC1 ((ADC_TypeDef *) ADC1_BASE)__DQ_FBIT__ 63USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)portBASE_TYPE longSPI_SR_BSY_Pos (7U)CAN_RDH0R_DATA6_Pos (16U)I2C_CR2_DMAEN_Pos (11U)ARM_MPU_RASR_EX(DisableExec,AccessPermission,AccessAttributes,SubRegionDisable,Size) ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))CAN_F9R1_FB23 CAN_F9R1_FB23_MskCAN_F1R2_FB6_Pos (6U)TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )ucDummy7BKP2RCAN_F3R1_FB28 CAN_F3R1_FB28_MskFSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)SysTick_CTRL_TICKINT_Pos 1URTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_MskFSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)SCB_SHCSR_SVCALLACT_Pos 7URCC_APB2ENR_TIM11EN_Pos (18U)LL_GPIO_AF_7 (0x0000007U)ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)ETH_MACDBGR_MTFCS_IDLE 0x00000000UGPIO_LCKR_LCK11 GPIO_LCKR_LCK11_MskFSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)CAN_F3R1_FB14_Pos (14U)ETH_WKUP_IRQn__unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__))FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLKconfigLIST_VOLATILE __set_BASEPRITIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)EXTI_IMR_IM21 EXTI_IMR_MR21TIM_CR2_OIS1 TIM_CR2_OIS1_MskADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)RCC_AHB1ENR_DMA1EN_Pos (21U)SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_MskGPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_MskSDIO_ICR_SDIOITC_Pos (22U)BKP3RCAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)_GLIBCXX98_USE_C99_COMPLEX 1__align_up(x,y) __builtin_align_up(x, y)__printf0like(fmtarg,firstvararg) USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)RNG_CR_RNGEN_Pos (2U)ETH_MACA1HR_MBC_LBits15_8 0x02000000UCAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)_PSTL_PRAGMA_FORCEINLINE GPIO_OSPEEDR_OSPEED15_0 0x40000000UCAN_F5R1_FB14 CAN_F5R1_FB14_MskGPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1traceSTREAM_BUFFER_CREATE_STATIC_FAILED(xReturn,xIsMessageBuffer) CAN_MSR_SLAK CAN_MSR_SLAK_MskDMA_LISR_HTIF3_Pos (26U)USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_MsktraceLOW_POWER_IDLE_END() CAN_F5R1_FB24_Pos (24U)CAN_F3R1_FB31_Pos (31U)CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_MskLL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WSUSB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)DCMI_DR_BYTE2 DCMI_DR_BYTE2_MskADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL )_GLIBCXX_DEBUG_ONLY(_Statement) ETH_PTPTSSR_TSSSR_Pos (9U)RCC_AHB2ENR_OTGFSEN_Pos (7U)ETH_DMABMR_DSL ETH_DMABMR_DSL_MskCAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)TIM_SR_CC2IF_Pos (2U)FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_MskTIM_CR2_CCDS_Pos (3U)GPIOD ((GPIO_TypeDef *) GPIOD_BASE)USB_OTG_DCFG_XCVRDLY_Pos (14U)CAN_FS1R_FSC11 CAN_FS1R_FSC11_MskETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)LL_GPIO_PIN_5 GPIO_BSRR_BS_5SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)CAN_F5R1_FB18_Pos (18U)SCS_BASE (0xE000E000UL)ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_MskLL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)_GLIBCXX_DEBUG_ASSERT(_Condition) ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)CAN_RF0R_FOVR0_Pos (4U)portDONT_DISCARD __attribute__( ( used ) )EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)DWT_SLEEPCNT_SLEEPCNT_Pos 0UBKP5RCAN_F4R2_FB10_Pos (10U)TIM_CCMR1_OC1CE_Pos (7U)EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)RTC_ISR_ALRBF RTC_ISR_ALRBF_MskADC_SMPR2_SMP8_Pos (24U)SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_MskCAN_ESR_TEC_Pos (16U)CAN_F12R1_FB9_Pos (9U)USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)DMA_LIFCR_CHTIF3_Pos (26U)USB_OTG_GOTGCTL_HNGSCS_Pos (8U)ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)GPIOI ((GPIO_TypeDef *) GPIOI_BASE)CAN_FM1R_FBM23 CAN_FM1R_FBM23_MskSPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN_GLIBCXX_HAVE_TANHF 1CAN_F10R1_FB27 CAN_F10R1_FB27_MskTIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4pvDummy1pvDummy2pvDummy3_GLIBCXX_PACKAGE__GLIBCXX_VERSION "version-unused"_PTRDIFF_T_DECLARED CAN_F7R1_FB28_Pos (28U)RTC_CR_TSIE RTC_CR_TSIE_MskRTC_CR_WUCKSEL_Pos (0U)I2C_OAR1_ADD4 I2C_OAR1_ADD4_MskMPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)CAN_F0R2_FB24 CAN_F0R2_FB24_MskDMA_SxCR_HTIE DMA_SxCR_HTIE_MskStaticListItem_tRTC_BKP12R_Pos (0U)ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_MskFSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)DMA_HISR_HTIF5 DMA_HISR_HTIF5_MskCAN_TSR_TXOK2 CAN_TSR_TXOK2_MskUSB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)CAN_F10R1_FB21_Pos (21U)USB_OTG_GOTGINT_ADTOCHG_Pos (18U)ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)__cpp_lib_logical_traits 201510LADC_SQR3_SQ6_Pos (25U)ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_MskETH_MACFFR_HU_Pos (1U)CAN_TSR_RQCP0_Pos (0U)SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)RCC_AHB2LPENR_RNGLPEN_Pos (6U)RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)LL_TIM_DIER_UIE TIM_DIER_UIE_GLIBCXX_HAVE_FMODF 1SYSCFG_EXTICR1_EXTI2_PH 0x00000700UEXTI_EMR_MR14_Pos (14U)SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)RCC_AHB1RSTR_CRCRST_Pos (12U)ADC_CSR_EOC2_Pos (9U)CAN_F13R2_FB7_Pos (7U)BKP7RDWT_CTRL_LSUEVTENA_Pos 20UCAN_FM1R_FBM9_Pos (9U)FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)__LACCUM_IBIT__ 32WUTRCAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)CAN_F6R2_FB14_Pos (14U)FSMC_BWTR2_DATAST_Pos (8U)CAN_F1R1_FB7_Pos (7U)FSMC_BTR1_ADDHLD_Pos (4U)CAN_F12R1_FB16 CAN_F12R1_FB16_MskCAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)CAN_F9R2_FB15 CAN_F9R2_FB15_MskCAN_F10R1_FB15_Pos (15U)USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_MskRCC_CSR_LSION_Pos (0U)I2C_CR1_START I2C_CR1_START_MskCAN_F2R2_FB10 CAN_F2R2_FB10_MskGPIO_BSRR_BR15 0x80000000URCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)TPI_DEVTYPE_SubType_Msk (0xFUL )CAN_F7R1_FB4_Pos (4U)RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Mskg_pfnVectors_crashCAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)USB_OTG_DCTL_CGINAK_Pos (8U)CAN_F12R1_FB31_Pos (31U)RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_MskDMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk__cpp_lib_addressof_constexpr 201603LRTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPSETH_MACDBGR_TFRS_READ_Pos (20U)BKP8RCAN_FM1R_FBM_Pos (0U)_GLIBCXX_NUMBERS 1LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)CAN_F4R1_FB6_Pos (6U)SDIO_MASK_TXFIFOHEIE_Pos (14U)DCMI_ESCR_LEC_Pos (16U)ADC_SQR1_SQ13_Pos (0U)SCB_SHCSR_USGFAULTENA_Pos 18UGPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)USB_OTG_GUSBCFG_ULPICSM_Pos (19U)DMA_SxCR_PINCOS_Pos (15U)INCLUDE_vTaskPrioritySet 1USART_CR1_PS USART_CR1_PS_Msk__cust_accessDMA_HIFCR_CFEIF5_Pos (6U)GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1USART_SR_IDLE USART_SR_IDLE_MskRCC_APB1LPENR_TIM4LPEN_Pos (2U)I2C_SR1_PECERR_Pos (12U)TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)ADC_JOFR1_JOFFSET1_Pos (0U)FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_MskCAN_F9R1_FB30 CAN_F9R1_FB30_MskCAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)_REENT_STDOUT(_ptr) ((_ptr)->_stdout)FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)BKP9RUSB_OTG_GOTGCTL_HSHNPEN_Pos (10U)pcTaskGetTaskName pcTaskGetNameTIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)SDIO_DCTRL_DBLOCKSIZE_Pos (4U)RTC_CR_FMT_Pos (6U)SPI_SR_TXE SPI_SR_TXE_MskUSB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_MskRCC_AHB2LPENR_OTGFSLPEN_Pos (7U)CAN_F8R2_FB18_Pos (18U)GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MISFSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)USB_OTG_DCTL_SDIS_Pos (1U)RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_MskI2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)FSMC_BCR1_WREN FSMC_BCR1_WREN_MskCAN_F0R1_FB23 CAN_F0R1_FB23_MskEXTI_RTSR_TR5 EXTI_RTSR_TR5_MskUSB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)ETH_MACA0LR_MACA0L_Pos (0U)INT_LEAST32_MAX __INT_LEAST32_MAX__SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)LL_GPIO_AF_6 (0x0000006U)EXTI_EMR_MR21 EXTI_EMR_MR21_MskUSB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk__UINT8_C(c) cDCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)__SIZEOF_LONG_LONG__ 8DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)CAN_F1R1_FB3 CAN_F1R1_FB3_MskCAN_F10R2_FB9_Pos (9U)MultiTempRequestRCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)SYSCFG_EXTICR2_EXTI7_PA 0x00000000UAHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3SYSCFG_EXTICR2_EXTI6_PC 0x00000200UUSB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_MskCAN_F7R2_FB28 CAN_F7R2_FB28_MsktraceGIVE_MUTEX_RECURSIVE(pxMutex) pdFREERTOS_ERRNO_ENOENT 2CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_MskCAN_F5R1_FB21 CAN_F5R1_FB21_MskRTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)__glibcxx_requires_subscript(_N) LL_DMA_STREAM_2 0x00000002UEXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)UART_DMA_Channel LL_DMA_CHANNEL_5CAN_F8R2_FB28 CAN_F8R2_FB28_MskCAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)configUSE_ALTERNATIVE_API 0CAN_F1R2_FB23 CAN_F1R2_FB23_MskCAN_F0R1_FB25_Pos (25U)GPIO_MODER_MODER5 GPIO_MODER_MODER5_MskCAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_MskRTC_ALRMBR_PM_Pos (22U)LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000UUSB_OTG_HCTSIZ_XFRSIZ_Pos (0U)DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)WWDG_CFR_W0 WWDG_CFR_W_0PWR_CSR_SBF PWR_CSR_SBF_MskCAN_FFA1R_FFA2_Pos (2U)ADC_JDR4_JDATA_Pos (0U)LL_UTILS_HSEBYPASS_ON 0x00000001U_GLIBCXX_NOTHROW _GLIBCXX_USE_NOEXCEPTDMA_LISR_DMEIF3_Pos (24U)CAN_F13R2_FB21_Pos (21U)FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_MskDMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)SYSCFG_EXTICR3_EXTI11_PF 0x00005000URTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)GPIO_MODER_MODE0_0 0x00000001U__pure __attribute__((__pure__))RCC_AHB1LPENR_GPIOILPEN_Pos (8U)CAN_F6R2_FB27 CAN_F6R2_FB27_MskCAN_FM1R_FBM18_Pos (18U)FSMC_SR4_IFEN_Pos (5U)RCC_CIR_LSIRDYIE_Pos (8U)ETH_PTPTSCR_TSCNT_Pos (16U)CAN_F1R1_FB12 CAN_F1R1_FB12_MskFSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_MskTIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_MskCAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASKCAN_FFA1R_FFA1 CAN_FFA1R_FFA1_MskCAN_F4R2_FB19 CAN_F4R2_FB19_MskCAN_F13R2_FB15_Pos (15U)LL_DMA_PERIPH_NOINCREMENT 0x00000000U__LDBL_MAX_10_EXP__ 308__GXX_ABI_VERSION 1018CAN_TDT0R_DLC_Pos (0U)__UQQ_IBIT__ 0DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk_POSIX_C_SOURCE 200809LADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)CAN_F12R1_FB4_Pos (4U)FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)__SIZE_T USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_MskUSB_OTG_HCCHAR_CHDIS_Pos (30U)USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)RCC_AHB1RSTR_OTGHRST_Pos (29U)FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)listLIST_IS_INITIALISED(pxList) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODENEXTI_RTSR_TR4_Pos (4U)FSMC_BWTR2_ADDHLD_Pos (4U)USB_OTG_GCCFG_VBUSASEN_Pos (18U)__GNUG__ 13USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | GPIO_BSRR_BS_15)CAN_F2R2_FB6_Pos (6U)LSI_STARTUP_TIME 40USYSCFG_EXTICR1_EXTI0_Pos (0U)__GCC_ATOMIC_LONG_LOCK_FREE 2RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)CAN_TDT1R_DLC CAN_TDT1R_DLC_MskINCLUDE_vTaskDelayUntil 0CAN_F3R2_FB27 CAN_F3R2_FB27_Msk__LLFRACT_MIN__ (-0.5LLR-0.5LLR)CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)CAN_F6R1_FB28 CAN_F6R1_FB28_Msk__alloc_size(x) __attribute__((__alloc_size__(x)))CAN_F7R1_FB4 CAN_F7R1_FB4_MskCAN_F1R2_FB21_Pos (21U)CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)__GNUC_VA_LIST_COMPATIBILITY 1RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_MskETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)GPIO_OSPEEDR_OSPEED3_0 0x00000040UTIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk_Kmax (sizeof (size_t) << 3)DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)CAN_FA1R_FACT16 CAN_FA1R_FACT16_MskSDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)GPIO_AFRL_AFSEL2_1 0x00000200UFSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)__XSI_VISIBLE 0_GLIBCXX14_DEPRECATED _GLIBCXX_DEPRECATEDFSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)ADC_SQR2_SQ8 ADC_SQR2_SQ8_MskLL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN_REENT_CLEANUP(_ptr) ((_ptr)->__cleanup)SYSCFG_EXTICR2_EXTI6_Pos (8U)USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)start_dmaing_rowADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)TIM_CCER_CC1NP TIM_CCER_CC1NP_MskFSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)CAN_F6R2_FB10_Pos (10U)CAN_F1R2_FB15_Pos (15U)USART_CR2_LBCL_Pos (8U)RTC_ISR_WUTF_Pos (10U)RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)_ZN5crash6Matrix16start_dmaing_rowEvEXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_MskFSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)EXTI_FTSR_TR12_Pos (12U)__cpp_nontype_template_parameter_auto 201606LCAN_F5R2_FB6 CAN_F5R2_FB6_MskCAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)TIM_CCR1_CCR1 TIM_CCR1_CCR1_MskCAN_F3R2_FB31_Pos (31U)__GXX_WEAK__ 1RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_MskCAN_F10R2_FB20 CAN_F10R2_FB20_MskTIM_CR2_OIS1N TIM_CR2_OIS1N_MskLL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)SYSCFG_EXTICR1_EXTI0_PA 0x00000000UCAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)SYSCFG_EXTICR3_EXTI12_PH 0x00000007UCAN_FM1R_FBM5 CAN_FM1R_FBM5_MskADC_SMPR2_SMP1 ADC_SMPR2_SMP1_MskLL_DMA_SetStreamPriorityLevelLL_TIM_IC_FILTER_FDIV1 0x00000000URCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)TIM_SMCR_ETPS TIM_SMCR_ETPS_MskCAN_F6R1_FB20 CAN_F6R1_FB20_MskCAN_F0R1_FB25 CAN_F0R1_FB25_MskINT64_MIN (-INT64_MAX - 1)GPIO_MODER_MODE5_0 0x00000400UADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)RCC_PLLCFGR_PLLP_Pos (16U)CAN_F9R2_FB27 CAN_F9R2_FB27_Msk/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/crash/main.cpp__CHAR32_TYPE__ long unsigned intETH_MACPMTCSR_WFE_Pos (2U)GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2CAN_F5R2_FB18_Pos (18U)USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_MskDMA_HISR_TEIF4 DMA_HISR_TEIF4_MskADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000CAN_F4R2_FB8 CAN_F4R2_FB8_MskUSB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_MskCAN_F3R1_FB14 CAN_F3R1_FB14_MskETH_DMASR_PMTS_Pos (28U)LL_TIM_ICPSC_DIV1 0x00000000UCAN_F10R1_FB20 CAN_F10R1_FB20_MskTPI_ITATBCTR2_ATREADY2_Pos 0UUSB_OTG_DIEPINT_BNA_Pos (9U)ranges__SIZEOF_FLOAT__ 4SDIO_MASK_CMDACTIE_Pos (11U)CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)USB_OTG_GINTMSK_FSUSPM_Pos (22U)ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)__ARM_FEATURE_BTIETH_MACA1HR_AE_Pos (31U)CAN_FS1R_FSC14_Pos (14U)USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_MskALRMARTIM3 ((TIM_TypeDef *) TIM3_BASE)UINT8_CEXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk__LDBL_HAS_DENORM__ 1USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)CAN_F9R1_FB16 CAN_F9R1_FB16_MskTIM_DIER_BIE_Pos (7U)__GNUCLIKE_ASM 3DCMI_ESUR_LEU_Pos (16U)_GLIBCXX_BEGIN_EXTERN_C extern "C" {ETH_DMASR_ROS ETH_DMASR_ROS_MskCAN_F2R1_FB11 CAN_F2R1_FB11_MskRCC_CSR_BORRSTF_Pos (25U)CAN_F8R1_FB13_Pos (13U)CAN_F11R1_FB20_Pos (20U)PERIPH_BB_BASE 0x42000000ULCAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_MskSCnSCB_ICTR_INTLINESNUM_Pos 0UI2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)ETH_DMABMR_EDE ETH_DMABMR_EDE_MskCAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)CAN_F5R2_FB18 CAN_F5R2_FB18_MskETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_MskADC_SQR3_SQ3 ADC_SQR3_SQ3_MskCAN_F11R1_FB29_Pos (29U)RAMFUNC __attribute__((externally_visible, section(".ram_func")))SCB_DFSR_HALTED_Pos 0U_GLIBCXX_FAST_MATH 0RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_MskUSB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_MskETH_PTPTSCR_TSSTI_Pos (2U)FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)ALRMBRSYSCFG_EXTICR3_EXTI10_PB 0x00000100UUSB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)USB_OTG_DIEPCTL_EPDIS_Pos (30U)USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_MskGPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10pdFREERTOS_ERRNO_EADDRINUSE 112CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)GPIO_MODER_MODER14 GPIO_MODER_MODER14_MskUSART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)CAN_F10R2_FB2 CAN_F10R2_FB2_MskRCC_BDCR_BDRST_Pos (16U)ETH_MACMIIAR_CR_Div26_Pos (2U)__OM volatileTIM_OR_ITR1_RMP_Pos (10U)RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_MskFSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_MskCAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)DCMI_IER_LINE_IE DCMI_IER_LINE_IE_MskUSB_OTG_DEACHINT_OEP1INT_Pos (17U)DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_MskUSB_OTG_GUSBCFG_FHMOD_Pos (29U)TIM_SMCR_ETF TIM_SMCR_ETF_MskFSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)FSMC_BCR2_ASYNCWAIT_Pos (15U)USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)CAN_F2R1_FB7_Pos (7U)__INT_FAST8_TYPE__ intDMA_LIFCR_CDMEIF3_Pos (24U)SP_at_isrSCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)__SYSTEM_STM32F2XX_H __cpp_user_defined_literals 200809LCAN_F10R2_FB15_Pos (15U)RTC_CR_OSEL_Pos (21U)__DBL_EPSILON__ double(2.2204460492503131e-16L)USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRLEXTI_PR_PR3_Pos (3U)USART_CR2_LBDL_Pos (5U)UART_ENABLE_CALL LL_APB2_GRP1_EnableClockeTaskStateGet eTaskGetStateEXTI_EMR_MR4 EXTI_EMR_MR4_MskFSMC_PATT4_ATTHIZ4_Pos (24U)configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_MskI2C2_ER_IRQnI2C_OAR2_ENDUAL_Pos (0U)GPIO_IDR_ID1 0x00000002UADC_SQR1_SQ14 ADC_SQR1_SQ14_MskDCMI_MISR_OVF_MIS DCMI_MIS_OVR_MISUSB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)SCB_HFSR_FORCED_Pos 30UGPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_MskADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)LL_SYSCFG_EXTI_PORTG (uint32_t)6RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)__IOM volatileRTC_ISR_ALRAF RTC_ISR_ALRAF_MskETH_DMASR_RS_Pos (6U)CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)LL_MPU_REGION_NUMBER0 0x00UCAN_F13R1_FB10_Pos (10U)CAN_TSR_RQCP2 CAN_TSR_RQCP2_MskADC_CSR_AWD1 ADC_CSR_AWD1_MskMSN_CRASH_SRVD DCMI_CR_CRE_Pos (12U)CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)CAN_F8R1_FB29 CAN_F8R1_FB29_MskEXTI_EMR_MR1_Pos (1U)CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_MskCAN_F5R2_FB21_Pos (21U)CAN_F1R1_FB24 CAN_F1R1_FB24_MskCAN_TDH0R_DATA4 CAN_TDH0R_DATA4_MskGPIO_OTYPER_OT_5 GPIO_OTYPER_OT5GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3GPIO_BSRR_BR2 0x00040000UDCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_MskCAN_FM1R_FBM15 CAN_FM1R_FBM15_MskconfigNUM_THREAD_LOCAL_STORAGE_POINTERS 0DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_MskADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)CAN_F3R1_FB1 CAN_F3R1_FB1_MskCAN_F13R1_FB0_Pos (0U)CAN_F10R1_FB19 CAN_F10R1_FB19_MskUSB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)CAN_F2R2_FB1 CAN_F2R2_FB1_Msk__FLT_HAS_QUIET_NAN__ 1CAN_F12R2_FB5 CAN_F12R2_FB5_Msk__FLT32X_MAX__ 1.7976931348623157e+308F32xCAN_F9R1_FB4_Pos (4U)CAN_F6R2_FB12 CAN_F6R2_FB12_MskETH_MACA2HR_SA_Pos (30U)DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)CAN_F12R2_FB19_Pos (19U)USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)_Nonnull CAN_F13R2_FB25 CAN_F13R2_FB25_MskETH_DMAIER_TJTIE_Pos (3U)RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1RNG_SR_SECS_Pos (2U)ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)GPIO_PUPDR_PUPD10_1 0x00200000UEXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)SPI_CR1_CRCEN_Pos (13U)RTC_CR_WUTIE RTC_CR_WUTIE_MskpdFREERTOS_ERRNO_ECANCELED 140__WINT_MIN__ 0UTIM_DCR_DBL_Pos (8U)USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_MskTIM_SMCR_ECE_Pos (14U)USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)GPIO_MODER_MODER15_Pos (30U)PWR_CSR_BRR PWR_CSR_BRR_MskCAN_F1R2_FB3 CAN_F1R2_FB3_MskRCC_APB2ENR_USART1EN_Pos (4U)TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)DBGMCU_CR_DBG_SLEEP_Pos (0U)SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)USB_OTG_DAINT_IEPINT_Pos (0U)CAN_F1R1_FB10_Pos (10U)EXTI_FTSR_TR11 EXTI_FTSR_TR11_MskDMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)__cpp_static_assert 201411LDWT_CTRL_NOEXTTRIG_Pos 26UPin<1073873920, 5>EXTI_SWIER_SWIER6_Pos (6U)FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_MskEXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)USB_OTG_DCTL_GINSTS_Pos (2U)priorityUSB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk__HAVE_SPECULATION_SAFE_VALUE 1WWDG_CR_T2 WWDG_CR_T_2DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)PINS_H RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)TPI_ITATBCTR2_ATREADY1_Pos 0UGPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)USART3 ((USART_TypeDef *) USART3_BASE)CAN_F11R1_FB18 CAN_F11R1_FB18_MskUSB_OTG_DOEPINT_NYET_Pos (14U)SYSCFG_EXTICR4_EXTI13_PA 0x00000000U_ZN5crash19print_wrapped_linesEPKchtCAN_F8R1_FB7 CAN_F8R1_FB7_Msk__GLIBCXX__ 20240614CAN_F0R2_FB19_Pos (19U)CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)DMA_SxCR_EN DMA_SxCR_EN_MskCAN_F3R1_FB20_Pos (20U)FSMC_SR3_ILEN FSMC_SR3_ILEN_MskCAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_MskRTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk_BSD_WCHAR_T___STDC_HOSTED__ 0RCC_APB1RSTR_I2C2RST_Pos (22U)CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)CAN_F12R2_FB15 CAN_F12R2_FB15_MskETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_MskDMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)CAN_FA1R_FACT24_Pos (24U)make_op(x) color_t operator x(const color_t& other) const {return color_t(r x other.r, g x other.g, b x other.b);} color_t& operator x ##= (const color_t& other) {r x ##= other.r; g x ##= other.g; b x ##= other.b; return *this;}DMA_HISR_DMEIF4_Pos (2U)USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)xSemaphoreGiveRecursive(xMutex) xQueueGiveMutexRecursive( ( xMutex ) )DCMI_ESCR_FSC DCMI_ESCR_FSC_MskI2C_SR2_GENCALL_Pos (4U)EXTI2_IRQnRCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)ETH_DMASR_RBUS_Pos (7U)ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)ETH_MMC_BASE (ETH_BASE + 0x0100UL)tskMPU_REGION_READ_WRITE ( 1UL << 1UL )ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_MskUSB_OTG_GUSBCFG_PHYSEL_Pos (6U)CAN_F5R2_FB25 CAN_F5R2_FB25_MskFLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)_GLIBCXX_VISIBILITY(V) __attribute__ ((__visibility__ (#V)))__ULFRACT_IBIT__ 0DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_MskCAN_F2R2_FB29_Pos (29U)RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_MskGPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)GPIO_BSRR_BR0 0x00010000UTPI_ITATBCTR0_ATREADY2_Msk (0x1UL )RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)CAN_F5R1_FB30_Pos (30U)RCC_APB2RSTR_TIM1RST_Pos (0U)TIM_CCER_CC4P_Pos (13U)CAN_F9R2_FB29 CAN_F9R2_FB29_MskFSMC_BTR3_DATLAT_Pos (24U)ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)DMA_LIFCR_CFEIF3_Pos (22U)__cpp_lib_remove_cvref 201711LUSB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)MMFRNVIC_SRV_RX_CLRF LL_DMA_ClearFlag_TC1CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)CAN_F11R2_FB10 CAN_F11R2_FB10_MskETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_MskUSB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_MskDMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)LL_GPIO_PIN_10 GPIO_BSRR_BS_10MSN_UIB_H CAN_F7R1_FB17_Pos (17U)__TA_IBIT__ 64LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)ADC_CDR_RDATA_SLV ADC_CDR_DATA2FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_MskCAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)CAN_F7R2_FB11 CAN_F7R2_FB11_MskTIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)CAN_F7R2_FB4_Pos (4U)CAN_F1R2_FB16 CAN_F1R2_FB16_Msk__SACCUM_EPSILON__ 0x1P-7HK_HAVE_LONG_DOUBLE 1CAN_F10R1_FB1 CAN_F10R1_FB1_MskDMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)USB_OTG_DIEPINT_AHBERR_Pos (2U)TIM_CCMR2_OC4M_Pos (12U)LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4ENFSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)RCC_APB1ENR_CAN1EN_Pos (25U)LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1LL_Init1msTickCAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)SDIO_CMD_WAITRESP_Pos (6U)CAN_F13R1_FB26 CAN_F13R1_FB26_MskTIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASKRTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_MskCAN_F9R1_FB27_Pos (27U)CAN_MCR_SLEEP CAN_MCR_SLEEP_MskDMA_HISR_TEIF6_Pos (19U)USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)SCB_SHCSR_MEMFAULTPENDED_Pos 13UCoreDebug_DHCSR_S_LOCKUP_Pos 19UGPIO_MODER_MODE10_1 0x00200000UCAN_IER_FFIE0_Pos (2U)DMA_HIFCR_CTCIF6_Pos (21U)CAN_F8R2_FB14 CAN_F8R2_FB14_MskDBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)I2C_CCR_FS_Pos (15U)DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)UINT64_MAXRCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)_Nullable CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_MskGPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)ADC_SMPR2_SMP2_Pos (6U)CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)__ARM_ARCH_PROFILE 77RCC_APB1ENR_USART3EN_Pos (18U)RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)CAN_F11R1_FB12 CAN_F11R1_FB12_MskDMA_SxCR_TEIE_Pos (2U)DWT_CTRL_NOCYCCNT_Pos 25UUSB_OTG_GINTSTS_IEPINT_Pos (18U)ClockDivisionETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk_STL_CONSTRUCT_H 1RCC_CSR_IWDGRSTF_Pos (29U)CAN_F8R1_FB31_Pos (31U)RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)ETH_MACSR_TSTS ETH_MACSR_TSTS_MskTPI_DEVID_NRZVALID_Pos 11USDIO_STA_TXFIFOE_Pos (18U)RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_MskLL_GPIO_MODE_INPUT (0x00000000U)ADC_SQR2_SQ9_Pos (10U)SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)RTC_DR_MT RTC_DR_MT_MskCAN_F6R2_FB7 CAN_F6R2_FB7_Msk__CORE_CM3_H_GENERIC GPIO_AFRH_AFSEL10_2 0x00000400U_REENT_CVTLEN(_ptr) ((_ptr)->_cvtlen)CAN_F12R1_FB21 CAN_F12R1_FB21_MskCAN_F8R2_FB13_Pos (13U)USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)CAN_F6R2_FB20_Pos (20U)CPACRFSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)CAN_F11R1_FB11 CAN_F11R1_FB11_MskETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_MskGPIO_AFRL_AFSEL6 0x0F000000UCAN_F12R1_FB15_Pos (15U)CAN_F12R1_FB14_Pos (14U)RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_MskTIM_CCMR2_CC3S TIM_CCMR2_CC3S_MskSDIO_STA_CMDSENT SDIO_STA_CMDSENT_MskRTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)__SVID_VISIBLE 1USB_OTG_GUSBCFG_FDMOD_Pos (30U)TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)CAN_F12R1_FB4 CAN_F12R1_FB4_MskEXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)BFARCAN_F0R1_FB8_Pos (8U)RCC_PLLCFGR_PLLM_Pos (0U)DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)TIM1_BRK_TIM9_IRQnCAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)RTC_ALRMAR_ST_Pos (4U)DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)CAN_F6R2_FB24 CAN_F6R2_FB24_MskI2C_OAR1_ADD9 I2C_OAR1_ADD9_MskEXTI_PR_PR3 EXTI_PR_PR3_MskOTG_HS_IRQnCAN_F0R2_FB29 CAN_F0R2_FB29_MskUSB_OTG_HCCHAR_DAD_Pos (22U)CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)GPIO_BSRR_BS10 0x00000400UpdFREERTOS_ERRNO_ENOMEDIUM 135FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)CAN_F5R1_FB29 CAN_F5R1_FB29_Msk__cpp_delegating_constructors 200604L__XSTRING(x) __STRING(x)FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)SCB_SHCSR_BUSFAULTACT_Pos 1UCAN_F8R2_FB30_Pos (30U)IS_UART_LIN_INSTANCE IS_UART_INSTANCECAN_F5R1_FB8 CAN_F5R1_FB8_MskCAN_F0R1_FB20_Pos (20U)USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_MskUSB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)pdFREERTOS_ERRNO_EEXIST 17USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_MskSPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)GPIO_BSRR_BS1 0x00000002UUSB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)EXTI_IMR_MR17_Pos (17U)CAN_F6R1_FB13 CAN_F6R1_FB13_MskCAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)__SACCUM_FBIT__ 7DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_MskCAN_F0R1_FB18 CAN_F0R1_FB18_MskI2C_SR1_RXNE I2C_SR1_RXNE_MskSCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)ETH_MACCR_IFG_88Bit 0x00020000UTIM_PSC_PSC_Pos (0U)TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)NbDataSDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)CAN_TDL2R_DATA2_Pos (16U)RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_MskRTC_TSDR_MT RTC_TSDR_MT_MskTIM_PSC_PSC TIM_PSC_PSC_MskUSB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)_ZN5crash6decode14fill_backtraceEPmRtmmmCAN_F2R2_FB15 CAN_F2R2_FB15_MskCAN_F1R2_FB27 CAN_F1R2_FB27_Mskpanic_nonfatalUSB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)xTaskNotifyWait(ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)__ARM_PCS 1USB_OTG_GINTSTS_DISCINT_Pos (29U)CAN_F11R2_FB6 CAN_F11R2_FB6_MskTPI_DEVTYPE_MajorType_Pos 0URCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)CAN_F11R1_FB1_Pos (1U)RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)_GLIBCXX_DOUBLE_IS_IEEE_BINARY64 1ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)CAN_F2R1_FB30_Pos (30U)__UINT_LEAST32_TYPE__ long unsigned intADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)I2C_SR2_DUALF_Pos (7U)CAN_F8R1_FB5 CAN_F8R1_FB5_MskCAN_F13R2_FB10_Pos (10U)CAN_F7R1_FB5_Pos (5U)CAN_FS1R_FSC6_Pos (6U)SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)gpio_initFSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)USB_OTG_HPRT_PSUSP_Pos (7U)ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_MskFSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_MskEXTI_RTSR_TR19_Pos (19U)ADC_JSQR_JSQ4_Pos (15U)SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)NDEBUG 1I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_MskCAN_F2R1_FB24_Pos (24U)LL_MPU_REGION_NUMBER4 0x04USDIO_STA_CEATAEND_Pos (23U)CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)RTC_BKP7R_Pos (0U)LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2_GLIBCXX_EXTERN_TEMPLATE 1__UQQ_FBIT__ 8CAN_F2R1_FB30 CAN_F2R1_FB30_MskUSB_OTG_GUSBCFG_PCCI_Pos (23U)_CONCEPT_CHECK_H 1CAN_F9R2_FB3_Pos (3U)__cpp_lib_transformation_trait_aliases 201304L__LDBL_DECIMAL_DIG__ 17CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)M0ARLL_DMA_STREAM_5 0x00000005UGPIO_MODER_MODE9_0 0x00040000UTPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)__DOTS , ...ETH_DMAOMR_RTC_96Bytes 0x00000010UCAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK)ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)SYSCFG_EXTICR2_EXTI6_PE 0x00000400UGPIO_BSRR_BR_1 GPIO_BSRR_BR1CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)__section(x) __attribute__((__section__(x)))CAN_F2R1_FB18_Pos (18U)_PSTL_PRAGMA_SIMD_ORDERED_MONOTONIC(PRM) RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_MskETH_DMABMR_AAB_Pos (25U)queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U )FSMC_BCR3_WRAPMOD_Pos (10U)TIM12 ((TIM_TypeDef *) TIM12_BASE)DMA_SxCR_DMEIE_Pos (1U)USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_MskCAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)SYSCFG_EXTICR4_EXTI12_PG 0x00000006U_GLIBCXX_ALGORITHMFWD_H 1RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_MskRCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_MskCAN_F1R2_FB10_Pos (10U)ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)CAN_RI0R_RTR CAN_RI0R_RTR_MskDAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_MskUSART_CR1_PS_Pos (9U)SDIO_MASK_CTIMEOUTIE_Pos (2U)DMA_LISR_DMEIF0_Pos (2U)RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()GPIO_BSRR_BR_5 GPIO_BSRR_BR5USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)ETH_MMCTIMR_TGFMSCM_Pos (15U)NVIC_SRV_TX_IRQ_NAME DMA2_Stream7_IRQnDMA_SxCR_ACK_Pos (20U)SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)GPIO_PUPDR_PUPD0_0 0x00000001UEXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)ETH_MACCR_BL_10 0x00000000UFSMC_SR4_IRS FSMC_SR4_IRS_MskCAN_F9R2_FB6 CAN_F9R2_FB6_MskCAN_FFA1R_FFA26_Pos (26U)USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12UETH_MMCCR_CSR ETH_MMCCR_CSR_MskADC_SQR3_SQ1_Pos (0U)WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)TIM_OR_TI1_RMP_Pos (0U)__STM32F207xx_H RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)CAN_F4R1_FB28_Pos (28U)ADC_CSR_EOC2 ADC_CSR_EOC2_MskTIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)__STDCPP_DEFAULT_NEW_ALIGNMENT__ 8SYSCFG_EXTICR4_EXTI14_PA 0x00000000U_GLIBCXX_HAVE_UTIME_H 1CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)CAN_FFA1R_FFA19_Pos (19U)ETH_MACDBGR_TFRS_WAITING_Pos (21U)__ATOMIC_RELAXED 0CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)GPIO_MODER_MODE3 0x000000C0UADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)tskKERNEL_VERSION_NUMBER "V10.4.0"SYSCFG_EXTICR1_EXTI2_Pos (8U)USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100UCAN_F3R2_FB25_Pos (25U)GPIO_AFRL_AFSEL0_0 0x00000001UUSB_OTG_FS_PERIPH_BASE 0x50000000ULCAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)traceEVENT_GROUP_DELETE(xEventGroup) CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)DCMI_MIS_FRAME_MIS_Pos (0U)CAN_F8R2_FB8 CAN_F8R2_FB8_MskxSemaphoreTakeFromISR(xSemaphore,pxHigherPriorityTaskWoken) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )CAN_F7R1_FB12 CAN_F7R1_FB12_MskETH_MACVLANTR_VLANTI_Pos (0U)CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)ARM_MPU_AP_PRIV 1UGPIO_OSPEEDR_OSPEED0_1 0x00000002U__ORDER_LITTLE_ENDIAN__ 1234FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_MskFSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_MskDMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)CAN_F3R2_FB14_Pos (14U)GPIO_MODER_MODE9 0x000C0000URCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)_REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)_REENT_MP_P5S(ptr) ((ptr)->_p5s)ITM_TCR_SWOENA_Pos 4UCAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)FSMC_PCR2_PWID_Pos (4U)GPIO_OSPEEDR_OSPEED13_0 0x04000000U_PTR_TRAITS_H 1IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS))CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)CAN_F5R2_FB30_Pos (30U)FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)CAN_F13R2_FB17 CAN_F13R2_FB17_MskFSMC_PCR4_ECCPS_Pos (17U)_GLIBCXX_USE_TBB_PAR_BACKEND __has_include()__CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB )SCB_SHCSR_BUSFAULTPENDED_Pos 14UI2C_SR1_SMBALERT I2C_SR1_SMBALERT_MskCAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)USB_OTG_DCTL_POPRGDNE_Pos (11U)RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)ADC_SQR2_SQ10_Pos (15U)USB_OTG_PCGCR_GATEHCLK_Pos (1U)DBGMCU_CR_TRACE_MODE_Pos (6U)ETH_DMASR_TPS_Closing_Pos (20U)configRECORD_STACK_HIGH_ADDRESS 0FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)configUSE_QUEUE_SETS 0__ARM_FEATURE_PAC_DEFAULTGPIO_MODER_MODE15 0xC0000000UUSB_OTG_HCINTMSK_NAKM_Pos (4U)ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)portLONG longportRESET_READY_PRIORITY(uxPriority,uxReadyPriorities) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )EXTI_EMR_MR9 EXTI_EMR_MR9_MskEXTI_FTSR_TR4 EXTI_FTSR_TR4_MskCAN_F5R2_FB24_Pos (24U)WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)NVIC_STIR_INTID_Pos 0UEXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)CAN_F10R2_FB18 CAN_F10R2_FB18_MskBKPSRAM_BB_BASE 0x42480000ULCAN_F11R1_FB18_Pos (18U)CAN_TDL1R_DATA0_Pos (0U)ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)__ISBADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)__cpp_lib_is_aggregate 201703LCAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)RTC_CR_TSEDGE RTC_CR_TSEDGE_MsktraceQUEUE_SEND_FROM_ISR_FAILED(pxQueue) TIM_CCMR2_OC4CE_Pos (15U)ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_MskFSMC_BCR4_MWID_Pos (4U)USB_OTG_DCFG_DSPD_Pos (0U)RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)LL_GPIO_PIN_6 GPIO_BSRR_BS_6char8_t__cpp_lib_constexpr_algorithms 201806LLL_APB2_GRP1_ReleaseResetEXTI_FTSR_TR0_Pos (0U)CAN_F5R1_FB6 CAN_F5R1_FB6_MskSDIO_CLKCR_NEGEDGE_Pos (13U)__LDBL_MIN_10_EXP__ (-307)_GLIBCXX_USE_TMPNAM 1DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk_ZN5crash6Matrix13start_displayEvFSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)DMA1_Stream2_IRQnxPortPendSVHandler PendSV_Handler__SFRACT_IBIT__ 0USART_SR_CTS USART_SR_CTS_MskRCC_APB1RSTR_UART4RST_Pos (19U)RTC_ALRMBR_WDSEL_Pos (30U)ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_MskCAN_F6R1_FB25 CAN_F6R1_FB25_MskINCLUDE_vTaskCleanUpResources 0CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)CAN_F13R1_FB9_Pos (9U)CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)GPIO_MODER_MODE7_0 0x00004000U_ZN5crash18show_backtrace_forEPKcmmmWWDG_CR_WDGA_Pos (7U)CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)DAC_SR_DMAUDR1_Pos (13U)GPIO_ODR_ODR_12 GPIO_ODR_OD12GPIO_AFRH_AFSEL10_3 0x00000800UGPIO_ODR_ODR_4 GPIO_ODR_OD4MSN_CRASH_RTOS_H FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_MskRCC_AHB1LPENR_GPIOELPEN_Pos (4U)CAN_F11R1_FB5 CAN_F11R1_FB5_MskTIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)INCLUDE_vTaskDelay 1DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)CAN_F7R2_FB28_Pos (28U)TIM5_IRQnLL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )ETH_DMASR_NIS_Pos (16U)EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)_GLIBCXX_HAVE_SYS_PARAM_H 1USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)__GCC_ATOMIC_SHORT_LOCK_FREE 2RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)CAN_F7R1_FB1 CAN_F7R1_FB1_MskSDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_MskRTC_CR_DCE_Pos (7U)CAN_F6R2_FB1 CAN_F6R2_FB1_MskCAN_F10R2_FB21_Pos (21U)CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)_PSTL_ICC_18_OMP_SIMD_BROKEN (__INTEL_COMPILER == 1800)RTC_CR_ALRAE_Pos (8U)_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)SYSCFG_EXTICR3_EXTI10_PD 0x00000300USPI_CR1_CPHA_Pos (0U)CAN_F11R1_FB29 CAN_F11R1_FB29_MskDMA_HISR_DMEIF7 DMA_HISR_DMEIF7_MskSPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)_GLIBCXX_HAVE_STRTOF 1__builtin_is_aligned(x,align) (((__uintptr_t)x & ((align) - 1)) == 0)FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)_REENT_CHECK_TM(ptr) DCMI_ESCR_FEC DCMI_ESCR_FEC_MskCAN_F13R2_FB1 CAN_F13R2_FB1_MskETH_DMASR_PMTS ETH_DMASR_PMTS_MskADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)__signed signedRTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)configGENERATE_RUN_TIME_STATS 0DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}CAN_F1R1_FB28_Pos (28U)xList List_tWWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_MskDMA2_Stream4_IRQnLL_DMA_MEMORY_INCREMENT DMA_SxCR_MINCRCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)__cmp_catDMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)RCC_APB1LPENR_DACLPEN_Pos (29U)PWR_CR_LPDS_Pos (0U)CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)READ_BIT(REG,BIT) ((REG) & (BIT))FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)CAN_F5R2_FB3 CAN_F5R2_FB3_MskconfigMAX_PRIORITIES (7)FSMC_PIO4_IOSET4_Pos (0U)CAN_F7R2_FB30 CAN_F7R2_FB30_MskCAN_F10R2_FB7 CAN_F10R2_FB7_MskLL_DMA_SetPeriphIncModeFSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_MskGPIO_MODER_MODER11_Pos (22U)SPI_CR1_CPOL_Pos (1U)GPIO_LCKR_LCK4_Pos (4U)ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)CAN_FM1R_FBM20 CAN_FM1R_FBM20_MskDMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_MskCAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)CAN_TSR_RQCP1_Pos (8U)USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)magicCAN_F10R1_FB24 CAN_F10R1_FB24_MskSCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)INT_FAST32_MIN (-INT_FAST32_MAX - 1)CAN_F10R1_FB10_Pos (10U)USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)ETH_PTPTSSR_TSSMRME_Pos (15U)FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)CAN_F13R1_FB18 CAN_F13R1_FB18_MskCAN_F13R1_FB8 CAN_F13R1_FB8_MsktraceQUEUE_CREATE(pxNewQueue) APB2RSTR__glibcxx_max_exponent10_GLIBCXX_CONSTEXPR constexprportCONFIGURE_TIMER_FOR_RUN_TIME_STATS() WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)ETH_DMASR_TBUS_Pos (2U)CAN_F0R2_FB14_Pos (14U)ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)RCC_CSR_PORRSTF RCC_CSR_PORRSTF_MskCAN_F12R2_FB25_Pos (25U)WEATHERRCC_CSR_BORRSTF RCC_CSR_BORRSTF_MskRCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)__cpp_aggregate_nsdmi 201304LDWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)CAN_F12R1_FB1_Pos (1U)TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_MskRCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000USYSCFG_EXTICR2_EXTI7_Pos (12U)FSMC_PATT3_ATTHIZ3_Pos (24U)__FLT32X_DIG__ 15ITM_TCR_TSPrescale_Pos 8UCAN_F8R1_FB5_Pos (5U)RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)CAN_F3R2_FB21 CAN_F3R2_FB21_MskFSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_MskFSMC_BCR1_EXTMOD_Pos (14U)GPIO_BSRR_BS3 0x00000008UCAN_ESR_EPVF CAN_ESR_EPVF_MskDAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000UCAN_FS1R_FSC1 CAN_FS1R_FSC1_MskI2C_SR1_AF I2C_SR1_AF_MskDMA_LISR_TCIF2_Pos (21U)CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)GPIO_AFRH_AFSEL9_1 0x00000020UI2C_CR1_PEC_Pos (12U)GPIO_AFRL_AFSEL7_3 0x80000000UETH_MMCCR_MCF ETH_MMCCR_MCF_MskSDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)MPU_RNR_REGION_Pos 0UFLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)GPIO_AFRH_AFSEL15_3 0x80000000U_PSTL_PRAGMA_MESSAGE(x) __WINT_WIDTH__ 32USART_SR_IDLE_Pos (4U)CAN_F12R1_FB13 CAN_F12R1_FB13_MskFSMC_BTR2_ADDSET_Pos (0U)ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_MskWWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)CAN_FA1R_FACT13_Pos (13U)USB_OTG_DIEPINT_INEPNE_Pos (6U)ETH_DMASR_TUS_Pos (5U)ETH_MACMIIDR_MD_Pos (0U)ETH_DMACHTDR_HTDAP_Pos (0U)CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)RCC_AHB2LPENR_DCMILPEN_Pos (0U)FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_MskDWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)CAN_F3R1_FB10 CAN_F3R1_FB10_Msk__ARM_FEATURE_NUMERIC_MAXMINADC ADC123_COMMONCAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)RCC_CIR_PLLI2SRDYF_Pos (5U)_GLIBCXX_USE_C99_COMPLEX_TR1 1CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)FSMC_BCR1_WRAPMOD_Pos (10U)CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)TIM1_TRG_COM_TIM11_IRQnRCC_AHB1LPENR_GPIOALPEN_Pos (0U)ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI( x )USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_MskCAN_FM1R_FBM1_Pos (1U)CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)CAN_F2R2_FB18_Pos (18U)FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)CAN_FA1R_FACT5 CAN_FA1R_FACT5_MskGPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0CAN_F6R2_FB14 CAN_F6R2_FB14_Msk__lock_try_acquire(lock) __retarget_lock_try_acquire(lock)ADC_CR1_AWDIE_Pos (6U)RCC_AHB1ENR_GPIOGEN_Pos (6U)CAN_F12R2_FB20 CAN_F12R2_FB20_MskCAN_FFA1R_FFA22 CAN_FFA1R_FFA22_MskDMA2_Stream1_BASE (DMA2_BASE + 0x028UL)SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)FLASH_CR_PG FLASH_CR_PG_MskTIM_CCMR1_IC1PSC_Pos (2U)__RAND_MAX 0x7fffffffGPIO_LCKR_LCK9 GPIO_LCKR_LCK9_MskDMA_LIFCR_CTCIF2_Pos (21U)RTC_ALRMBR_SU RTC_ALRMBR_SU_MskGPIO_OTYPER_OT6 0x00000040UIS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM10)|| ((INSTANCE) == TIM11)|| ((INSTANCE) == TIM12)|| ((INSTANCE) == TIM13)|| ((INSTANCE) == TIM14))CAN_F1R1_FB5 CAN_F1R1_FB5_MskWWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)CAN_F0R2_FB5 CAN_F0R2_FB5_Mskcreate_PSTL_CPP11_STD_ROTATE_BROKEN ((__GLIBCXX__ && __GLIBCXX__ < 20150716) || (_MSC_VER && _MSC_VER < 1800))USB_OTG_DIEPCTL_EPENA_Pos (31U)ETH_DMAOMR_FEF ETH_DMAOMR_FEF_MskTIM_CCMR2_OC3FE_Pos (2U)ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_MskCAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_MskUSB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)CAN_IER_EPVIE_Pos (9U)USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)CAN_F4R2_FB28_Pos (28U)SCB_SHCSR_SYSTICKACT_Pos 11UFSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_MskTIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)SDIO_DCTRL_RWMOD_Pos (10U)RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)LL_GPIO_PIN_15 GPIO_BSRR_BS_15ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk__cpp_designated_initializers 201707L__UDA_IBIT__ 32CAN_F0R1_FB7 CAN_F0R1_FB7_MskUSB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)deadzoneDMA_HISR_FEIF6_Pos (16U)RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)TIM_DIER_TIE TIM_DIER_TIE_Msk__UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)pdTRUE ( ( BaseType_t ) 1 )CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_MskEXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_MskCAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)__GNUCLIKE_BUILTIN_VAALIST 1CAN_F3R2_FB6_Pos (6U)ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)RTC_BKP7R RTC_BKP7R_MskCAN_F9R1_FB16_Pos (16U)RTC_CR_ALRAE RTC_CR_ALRAE_MskCAN_F7R1_FB23_Pos (23U)RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_MskEXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)cancellableFSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)LL_DMA_MBURST_SINGLE 0x00000000UDMA_SxCR_DBM DMA_SxCR_DBM_MskDT_RANGE_2 ((uint8_t)0x80)SCB_HFSR_DEBUGEVT_Pos 31U__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))USB_OTG_HCINTMSK_ACKM_Pos (5U)CAN_F2R1_FB23 CAN_F2R1_FB23_MskETH_MACA2HR_AE ETH_MACA2HR_AE_MskADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk_BEGIN_STD_C extern "C" {USB_OTG_GINTMSK_SRQIM_Pos (30U)ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)RCC_APB2LPENR_TIM8LPEN_Pos (1U)__PACKED_STRUCT struct __attribute__((packed, aligned(1)))ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)LL_DMA_ReadReg(__INSTANCE__,__REG__) READ_REG(__INSTANCE__->__REG__)CAN_F13R1_FB31 CAN_F13R1_FB31_MskWWDG_CFR_EWI_Pos (9U)GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)_GLIBCXX_DEPRECATED __attribute__ ((__deprecated__))TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_MskUSB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)RTC_ISR_ALRAWF RTC_ISR_ALRAWF_MskCAN_RDL1R_DATA0_Pos (0U)TPI_FFSR_FlInProg_Msk (0x1UL )LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)RCC_CIR_CSSC RCC_CIR_CSSC_MskUSB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_MskADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)RCC_APB1RSTR_CAN1RST_Pos (25U)USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)CAN_F0R1_FB29 CAN_F0R1_FB29_MskRNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)RTC_ISR_WUTF RTC_ISR_WUTF_MskCAN_F5R1_FB19 CAN_F5R1_FB19_MskCAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)ADC_CSR_EOC3 ADC_CSR_EOC3_MskGPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0RTC_CR_TSEDGE_Pos (3U)WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)CAN_F7R2_FB16 CAN_F7R2_FB16_Msk__UHQ_IBIT__ 0DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)FLASH_SR_PGPERR_Pos (6U)EXTI_IMR_MR12_Pos (12U)FSMC_BCR1_BURSTEN_Pos (8U)ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_MskEXTI_IMR_MR10 EXTI_IMR_MR10_MskCAN_F10R1_FB6 CAN_F10R1_FB6_MskLL_GPIO_PIN_7 GPIO_BSRR_BS_7RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk__OBSOLETE_MATH_DEFAULT 1FSMC_BWTR3_ADDSET_Pos (0U)UINT_FAST64_MAXAHB3ENRGPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)EXTI_IMR_IM7 EXTI_IMR_MR7RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_MskRTC_BKP18R RTC_BKP18R_MskxTaskNotifyAndQueryIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )RTC_ALRMAR_WDSEL_Pos (30U)CAN_F5R2_FB4_Pos (4U)SIMPLMATRIX_H FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)UINT32_MAXUSB_OTG_GINTSTS_RXFLVL_Pos (4U)USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)listGET_LIST_ITEM_OWNER(pxListItem) ( ( pxListItem )->pvOwner )SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)USART_SR_RXNE USART_SR_RXNE_MskEXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)_PSTL_USAGE_WARNINGS 0DCMI_CR_EDM_1 0x00000800UETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)__cpp_lib_constexpr_utility 201811LFLASH_ACR_ICEN FLASH_ACR_ICEN_MskCAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)CAN_F13R1_FB1_Pos (1U)RCC_APB1ENR_USART2EN_Pos (17U)NotSetCAN_F7R1_FB31 CAN_F7R1_FB31_MskUSB_OTG_GRSTCTL_HSRST_Pos (1U)RCC_APB2RSTR_SYSCFGRST_Pos (14U)FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)EXTI_RTSR_TR14_Pos (14U)GPIO_MODER_MODER1 GPIO_MODER_MODER1_MskRCC_APB2ENR_USART6EN_Pos (5U)CAN_F11R2_FB29_Pos (29U)__STM32F2xx_LL_UTILS_H SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_MskUSB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_MskCAN_FA1R_FACT19 CAN_FA1R_FACT19_MskFSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)fill_backtraceADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_MskUSB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)__LDBL_MANT_DIG__ 53TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)LL_GPIO_PIN_12 GPIO_BSRR_BS_12SDIO_CMD_NIEN SDIO_CMD_NIEN_MskCAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)__SIZEOF_PTRDIFF_T__ 4I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)I2C_SR1_ADDR_Pos (1U)ETH_DMAOMR_DFRF_Pos (24U)RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)FSMC_BWTR4_DATAST_1 (0x02UL << FSMC_BWTR4_DATAST_Pos)RTC_CR_ALRAIE_Pos (12U)DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)traceTASK_NOTIFY_FROM_ISR(uxIndexToNotify) TIM2 ((TIM_TypeDef *) TIM2_BASE)13FLASH_TypeDefDCMI_ESUR_FSU_Pos (0U)CAN_F2R1_FB13_Pos (13U)ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_MskI2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)GPIO_ODR_OD11 0x00000800UFSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)SubPriorityBitsCAN_F3R1_FB7_Pos (7U)_PSTL_HIDE_FROM_ABI_POP CAN_F12R1_FB9 CAN_F12R1_FB9_MskUSB_OTG_HCINT_NAK_Pos (4U)CoreDebug_DEMCR_VC_MMERR_Pos 4U__STM32F2xx_LL_TIM_H USART_CR1_PCE USART_CR1_PCE_MskI2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)EXTI_IMR_MR22 EXTI_IMR_MR22_MskCAN_FA1R_FACT4_Pos (4U)ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)EXTI_FTSR_TR4_Pos (4U)EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)UINT8_MAX __UINT8_MAX__ADC_CR1_RES_Pos (24U)FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)SYSCFG_EXTICR3_EXTI9_PB 0x00000010UTIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_MskUSB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)configMIN(a,b) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )LL_TIM_COUNTERMODE_UP 0x00000000UCAN_F8R2_FB10 CAN_F8R2_FB10_MskFLASH_ACR_LATENCY_1WS 0x00000001UUSB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)CAN_F10R1_FB2_Pos (2U)USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)CAN_FM1R_FBM13_Pos (13U)GPIO_MODER_MODER4_Pos (8U)CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)CAN_FFA1R_FFA21_Pos (21U)RTC_ALRMAR_ST RTC_ALRMAR_ST_MskCAN_FA1R_FACT27 CAN_FA1R_FACT27_MskCAN_F6R1_FB6_Pos (6U)__INT64_TYPE__ long long intUSB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)CAN_F4R1_FB23_Pos (23U)I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)FSMC_BCR2_WAITEN_Pos (13U)FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)CAN_FS1R_FSC18 CAN_FS1R_FSC18_MskTPI_FFSR_FlInProg_Pos 0USDIO_MASK_CCRCFAILIE_Pos (0U)__EXP(x) __ ##x ##__USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_MskLL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)USART_CR2_LBDIE USART_CR2_LBDIE_MskSCB_ICSR_PENDSTSET_Pos 26UCAN_F6R1_FB18 CAN_F6R1_FB18_MskEXTI_IMR_IM EXTI_IMR_IM_MskCAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)USB_OTG_HPRT_PTCTL_Pos (13U)FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)EXTI_EMR_MR13 EXTI_EMR_MR13_MskTPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)LL_MPU_REGION_NUMBER5 0x05UCAN_F0R2_FB31_Pos (31U)AlternateGPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)USB_OTG_PKTSTS USB_OTG_PKTSTS_MskLL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN__UACCUM_FBIT__ 16FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_MskCAN_F4R1_FB17_Pos (17U)CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)USART_CR3_IREN_Pos (1U)DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)_DEFAULT_SOURCECAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)ETH_MACA3HR_SA_Pos (30U)ADC_CDR_RDATA_MST ADC_CDR_DATA1USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_MskTIM_CCMR1_OC2PE_Pos (11U)ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)LL_DMA_PRIORITY_LOW 0x00000000UCAN_IER_WKUIE CAN_IER_WKUIE_MskRTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U )CAN_TSR_TERR2 CAN_TSR_TERR2_MskGPIO_PUPDR_PUPD9_0 0x00040000UUSB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_MskRCC_BDCR_RTCSEL_Pos (8U)CAN_F12R2_FB9_Pos (9U)__LL_DMA_GET_STREAM(__STREAM_INSTANCE__) (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : LL_DMA_STREAM_7)__glibcxx_numbersFSMC_BCR4_EXTMOD_Pos (14U)CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)__glibcxx_numbers(TYPE,SUFFIX) template<> inline constexpr TYPE e_v = 2.718281828459045235360287471352662498 ##SUFFIX; template<> inline constexpr TYPE log2e_v = 1.442695040888963407359924681001892137 ##SUFFIX; template<> inline constexpr TYPE log10e_v = 0.434294481903251827651128918916605082 ##SUFFIX; template<> inline constexpr TYPE pi_v = 3.141592653589793238462643383279502884 ##SUFFIX; template<> inline constexpr TYPE inv_pi_v = 0.318309886183790671537767526745028724 ##SUFFIX; template<> inline constexpr TYPE inv_sqrtpi_v = 0.564189583547756286948079451560772586 ##SUFFIX; template<> inline constexpr TYPE ln2_v = 0.693147180559945309417232121458176568 ##SUFFIX; template<> inline constexpr TYPE ln10_v = 2.302585092994045684017991454684364208 ##SUFFIX; template<> inline constexpr TYPE sqrt2_v = 1.414213562373095048801688724209698079 ##SUFFIX; template<> inline constexpr TYPE sqrt3_v = 1.732050807568877293527446341505872367 ##SUFFIX; template<> inline constexpr TYPE inv_sqrt3_v = 0.577350269189625764509148780501957456 ##SUFFIX; template<> inline constexpr TYPE egamma_v = 0.577215664901532860606512090082402431 ##SUFFIX; template<> inline constexpr TYPE phi_v = 1.618033988749894848204586834365638118 ##SUFFIXSYSCFG_EXTICR2_EXTI6_PG 0x00000600UCAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U )CAN_F6R1_FB27_Pos (27U)TIM1_CC_IRQnRTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)_REENT_INIT_RESERVED_2 TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)CAN_TI0R_RTR CAN_TI0R_RTR_MskDMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)ADC_CSR_EOC3_Pos (17U)__cpp_lib_is_pointer_interconvertible 201907LEXTI_FTSR_TR9_Pos (9U)GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)EXTI_IMR_MR9 EXTI_IMR_MR9_MskSDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)CAN_F7R2_FB23 CAN_F7R2_FB23_MskCAN_F1R2_FB28 CAN_F1R2_FB28_MskUSB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)RTC_DR_YU RTC_DR_YU_MskDMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_MskGPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_MskTIM_CCR4_CCR4_Pos (0U)USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)pdFREERTOS_ERRNO_ENOMEM 12USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)CAN_F0R2_FB25_Pos (25U)CAN_FM1R_FBM12 CAN_FM1R_FBM12_MskFSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)GPIO_BSRR_BR_9 GPIO_BSRR_BR9GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1__UTA_IBIT__ 64CAN_MSR_RXM CAN_MSR_RXM_MskCAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)FLASH_CR_EOPIE_Pos (24U)USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)CAN_F9R1_FB8 CAN_F9R1_FB8_MskUSB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)RCC_CSR_LSIRDY_Pos (1U)EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_MskADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)CAN_F13R2_FB22 CAN_F13R2_FB22_MskDMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)CAN_F11R1_FB30_Pos (30U)TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)__FLT32_NORM_MAX__ 3.4028234663852886e+38F32MSN_BHEAP_INLINE_V const inline staticETH_MAC_BASE (ETH_BASE)RCC_CIR_LSERDYIE_Pos (9U)LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWRENDMA_LIFCR_CDMEIF0_Pos (2U)SDIO_MASK_CEATAENDIE_Pos (23U)RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_MskCAN_F3R2_FB14 CAN_F3R2_FB14_MskDMA_HIFCR_CDMEIF4_Pos (2U)RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)FLASH_ACR_LATENCY_5WS 0x00000005ULL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHENADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)__SFRACT_FBIT__ 7LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)__cpp_return_type_deduction 201304LCAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)__GCC_ATOMIC_CHAR_LOCK_FREE 2SCB_SHCSR_MEMFAULTACT_Msk (1UL )CAN_F10R2_FB23 CAN_F10R2_FB23_MskCAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)CAN_F7R2_FB23_Pos (23U)ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_MskSDIO_ICR_STBITERRC_Pos (9U)SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)DMA_LISR_HTIF1_Pos (10U)ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)GPIO_MODER_MODER0_Pos (0U)RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_MskSDIO_STA_DBCKEND_Pos (10U)SYSCFG_EXTICR1_EXTI1_PI 0x00000080UCAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)TIM_BDTR_AOE_Pos (14U)GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)PRIVILEGED_FUNCTION USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)__DA_IBIT__ 32TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)pdFREERTOS_ERRNO_EISDIR 21ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)11DMA_TypeDeftraceBLOCKING_ON_QUEUE_PEEK(pxQueue) CAN_F7R2_FB17_Pos (17U)CAN_IER_FOVIE1_Pos (6U)GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1SCB_SHCSR_USGFAULTACT_Pos 3UCAN_RDT0R_DLC CAN_RDT0R_DLC_MskRCC_BDCR_LSEBYP_Pos (2U)listGET_OWNER_OF_NEXT_ENTRY(pxTCB,pxList) { List_t * const pxConstList = ( pxList ); ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) { ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; } ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; }ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_MskCAN_F8R2_FB4_Pos (4U)CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)USART_SR_ORE USART_SR_ORE_MskSCB_ICSR_PENDSTCLR_Pos 25U__DBL_MIN__ double(2.2250738585072014e-308L)LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0RTC_ALRMAR_MNT_Pos (12U)EXTI_RTSR_TR22 EXTI_RTSR_TR22_MskUSART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_MskSTIRTIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)FSMC_BCR3_WAITCFG_Pos (11U)_GLIBCXX_HAVE_TGMATH_H 1RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)ETH_DMAOMR_DTCEFD_Pos (26U)CAN_F12R2_FB12 CAN_F12R2_FB12_MskUSB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_MskETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_MskRCC_CFGR_HPRE_DIV1 0x00000000U_ZN5crash4rtos13get_task_regsEPmRmS2_S2_DMA_LIFCR_CHTIF1_Pos (10U)RCC_AHB3RSTR_FSMCRST_Pos (0U)FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)CAN_F9R2_FB27_Pos (27U)CAN_F7R2_FB5 CAN_F7R2_FB5_MskRTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)CAN_TSR_RQCP1 CAN_TSR_RQCP1_MskUSB_OTG_HS_TOTAL_FIFO_SIZE 4096UETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_MskLL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4ENEXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)CAN_F1R1_FB17_Pos (17U)CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)CAN_F13R1_FB28_Pos (28U)DAC_CR_WAVE1 DAC_CR_WAVE1_MskI2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)CAN_F11R2_FB9_Pos (9U)RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_MskUSB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_MskGPIO_ODR_OD15 0x00008000UGPIO_AFRL_AFSEL0_3 0x00000008USYSCFG_EXTICR1_EXTI1_PG 0x00000060UWWDG_CFR_W1 WWDG_CFR_W_1CAN_F8R2_FB22 CAN_F8R2_FB22_Msk_GLIBCXX_HAVE_SINHF 1FSMC_BWTR3_DATAST_Pos (8U)CAN_F12R2_FB20_Pos (20U)FSMC_BTR2_ADDHLD_Pos (4U)USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_MskUSB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)DMA_LISR_HTIF1 DMA_LISR_HTIF1_MskI2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)__glibcxx_requires_heap(_First,_Last) GPIO_AFRL_AFSEL2 0x00000F00UUSB_OTG_DAINTMSK_OEPM_Pos (16U)xSemaphoreGetMutexHolder(xSemaphore) xQueueGetMutexHolder( ( xSemaphore ) )CAN2 ((CAN_TypeDef *) CAN2_BASE)FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_MskRTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)_GLIBCXX_PACKAGE_URL ""SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_MskETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_MskCAN_F11R2_FB29 CAN_F11R2_FB29_MskI2C_CCR_CCR I2C_CCR_CCR_Msk_GLIBCXX_HAVE_FCNTL_H 1USB_OTG_DIEPCTL_STALL_Pos (21U)USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_MskETH_MACCR_FES ETH_MACCR_FES_MskADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)__FLT64_EPSILON__ 2.2204460492503131e-16F64RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk_GLIBCXX_USE_LONG_LONG 1CAN_F8R1_FB11 CAN_F8R1_FB11_MskUSB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)ETH_DMAIER_TUIE_Pos (5U)SDIO_STA_RXFIFOF_Pos (17U)CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)__glibcxx_requires_string(_String) CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)CAN_F1R1_FB8_Pos (8U)SYSCFG_EXTICR3_EXTI10_PF 0x00000500U_GLIBCXX_PACKAGE_TARNAME "libstdc++"__UINT_LEAST64_MAX__ 0xffffffffffffffffULLETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_MskGPIO_BSRR_BR3 0x00080000UCAN_F11R2_FB28 CAN_F11R2_FB28_Msk__IEEE_LITTLE_ENDIAN CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)ulTaskNotifyTakeIndexed(uxIndexToWaitOn,xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( uxIndexToNotify ), ( xClearCountOnExit ), ( xTicksToWait ) )GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))CAN_F13R1_FB23 CAN_F13R1_FB23_MskEXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)SYSCFG_EXTICR4_EXTI12_Pos (0U)ADC_CR1_DISCNUM ADC_CR1_DISCNUM_MskCAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)EXTI_EMR_MR6 EXTI_EMR_MR6_MskRCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)DMA_SxFCR_FS_Pos (3U)SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_MskCAN_F0R2_FB20_Pos (20U)FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk_GLIBCXX_HAVE_BUILTIN_HAS_UNIQ_OBJ_REP 1CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)CAN_F11R2_FB27 CAN_F11R2_FB27_MskCAN_F4R1_FB7_Pos (7U)SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)CAN_F1R2_FB14 CAN_F1R2_FB14_Msk__HA_IBIT__ 8SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)ISARADC_SQR2_SQ11 ADC_SQR2_SQ11_MskCoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_MskRTC_CALIBR_DC RTC_CALIBR_DC_MskGPIO_MODER_MODE5_1 0x00000800UnotifyRTC_TAFCR_TAMP1TRG_Pos (1U)SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)ITM_IWR_ATVALIDM_Msk (1UL )_GLIBCXX_DEBUG_PEDASSERT(_Condition) DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_MskpdFREERTOS_ERRNO_EACCES 13ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)EXTI_EMR_EM16 EXTI_EMR_MR16RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_MskUSB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_MskRTC_BKP10R_Pos (0U)RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)CAN_F5R2_FB31_Pos (31U)ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)char32_tLL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOEDAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)UINT32_C(c) __UINT32_C(c)CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)SCB_CPUID_IMPLEMENTER_Pos 24UFSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)_GLIBCXX_HAVE_LIMIT_RSS 0LL_TIM_SR_BIF TIM_SR_BIFCAN_F2R2_FB30_Pos (30U)SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)_ZN5crash8delay_msEmbGPIO_MODER_MODER15 GPIO_MODER_MODER15_MskPERIPH_BASE 0x40000000ULTPI_ITCTRL_Mode_Pos 0UETH_DMAOMR_SR ETH_DMAOMR_SR_MskSPI_I2SPR_MCKOE_Pos (9U)CAN_F0R1_FB1_Pos (1U)CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)LOADADC_CR2_EOCS ADC_CR2_EOCS_MskTIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_MskRCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_MskETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)_POSIX_SOURCECAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)CAN_F8R1_FB30 CAN_F8R1_FB30_MskADC_CCR_DMA_Pos (14U)CAN_F4R2_FB17_Pos (17U)__FLT_EVAL_METHOD__ 0CAN_F2R2_FB24_Pos (24U)CAN_F7R1_FB24 CAN_F7R1_FB24_MskETH_DMABMR_PBL_16Beat 0x00001000UCAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)TIM_CCMR1_OC2FE_Pos (10U)CAN_F1R1_FB29 CAN_F1R1_FB29_MskUSART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_MskLL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFUARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)RTC_BKP17R_Pos (0U)RTC_TR_HU RTC_TR_HU_MskWWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)dummyreadAPB2ENRSYSCFG_EXTICR4_EXTI15_PG 0x00006000ULL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)DMA_SxCR_MBURST_Pos (23U)FSMC_PATT4_ATTHOLD4_Pos (16U)I2C_CCR_DUTY_Pos (14U)traceLOW_POWER_IDLE_BEGIN() TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)GPIO_PUPDR_PUPD3 0x000000C0USDIO_ICR_DTIMEOUTC_Pos (3U)CAN_TI1R_IDE_Pos (2U)DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)USB_OTG_GINTMSK_EPMISM_Pos (17U)FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)CAN_FFA1R_FFA3_Pos (3U)TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)RTC_CR_DCE RTC_CR_DCE_MskUSB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_MskCAN_F7R1_FB12_Pos (12U)TIM_ARR_ARR_Pos (0U)I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_MskDBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)18LL_TIM_InitTypeDefCAN_F6R2_FB27_Pos (27U)FLASH_CR_SER FLASH_CR_SER_MskETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_MskFSMC_PATT3_ATTSET3_Pos (0U)FSMC_BWTR3_ADDHLD_Pos (4U)SYSCFG_EXTICR4_EXTI15_PD 0x00003000USPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)CAN_F10R1_FB28_Pos (28U)DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_MskCAN_F5R1_FB30 CAN_F5R1_FB30_MskCAN_F9R1_FB10 CAN_F9R1_FB10_MskUSB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)CAN_F3R1_FB15 CAN_F3R1_FB15_MskUSB_OTG_HPTXSTS_PTXQSAV_Pos (16U)ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)ADC_CR2_JEXTEN_Pos (20U)EXTI_IMR_MR15 EXTI_IMR_MR15_MskUSB_OTG_GINTSTS_OTGINT_Pos (2U)GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1ENDT_RANGE_3 ((uint8_t)0xC0)NVIC_SRV_RX_ACTV LL_DMA_IsActiveFlag_TC1CAN_F2R2_FB5 CAN_F2R2_FB5_MskIS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))__LONG_LONG_WIDTH__ 64DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_MskETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)__INT_LEAST16_TYPE__ short intRCC_APB1RSTR_TIM13RST_Pos (7U)ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)ISERSRAM1_BASE 0x20000000ULUSB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_MskRCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_MskCAN_TDL1R_DATA3_Pos (24U)SYSCFG_EXTICR4_EXTI15_PA 0x00000000U_REENT_INIT_RESERVED_8 RCC_AHB1RSTR_GPIOERST_Pos (4U)USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)GPIO_ODR_OD8 0x00000100URCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_MskMPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)USB_OTG_HCINT_TXERR_Pos (7U)CAN_F8R1_FB30_Pos (30U)RTC_PRER_PREDIV_S_Pos (0U)EXTI_RTSR_TR5_Pos (5U)GPIO_OTYPER_OT0 0x00000001UTIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)CAN_F7R2_FB3 CAN_F7R2_FB3_Msk__GNUCLIKE_MATH_BUILTIN_CONSTANTS TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)__ATOMIC_SEQ_CST 5_PSTL_VERSION_MINOR ((_PSTL_VERSION % 1000) / 10)__ARM_FEATURE_CDEINT32_C(c) __INT32_C(c)RCC_APB1ENR_TIM7EN_Pos (5U)CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)ETH_MMCTIR_TGFS_Pos (21U)USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_MskLL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOPUSB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)RTC_CR_ALRAIE RTC_CR_ALRAIE_MskSDIO_ICR_DBCKENDC_Pos (10U)ETH_MACA3HR_SA ETH_MACA3HR_SA_MskDCMI_CR_VSPOL DCMI_CR_VSPOL_MskCAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)RESERVEDRCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)TypeDumpLogOutCAN_F0R1_FB11_Pos (11U)ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)FLASH_CR_SNB FLASH_CR_SNB_MskUSB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)CAN_F10R2_FB1_Pos (1U)GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)EXTI_RTSR_TR0_Pos (0U)FSMC_BTR4_BUSTURN_Pos (16U)FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)CAN_F4R2_FB20 CAN_F4R2_FB20_MskDCMI_ESCR_LSC_Pos (8U)CAN_F11R2_FB24_Pos (24U)GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)SysTick_CALIB_SKEW_Pos 30Ustart_displayFLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)TIM_BDTR_MOE TIM_BDTR_MOE_MskETH_DMATPDR_TPD_Pos (0U)CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U_REENT_STDERR(_ptr) ((_ptr)->_stderr)CAN_F2R1_FB0 CAN_F2R1_FB0_MskDMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)_GLIBCXX_HAVE_STRERROR_R 1USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)CAN_MCR_TXFP CAN_MCR_TXFP_MskCAN_F1R2_FB0 CAN_F1R2_FB0_MskADC_CSR_OVR3 ADC_CSR_OVR3_MskETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_MskCAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)pdFREERTOS_ERRNO_NONE 0EXTI_IMR_IM_Pos (0U)CAN_F13R2_FB0_Pos (0U)CAN_F2R1_FB28 CAN_F2R1_FB28_MskUSB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_MskTIM_CR2_OIS3N_Pos (13U)SCB_ICSR_RETTOBASE_Pos 11UADC_SQR2_SQ12_Pos (25U)CAN_F11R2_FB25 CAN_F11R2_FB25_MskRCC_AHB1LPENR_ETHMACLPEN_Pos (25U)CAN_F9R2_FB4_Pos (4U)SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk__FLT32_MIN_10_EXP__ (-37)WWDG_CFR_WDGTB WWDG_CFR_WDGTB_MskEXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)DMA_LISR_TEIF0 DMA_LISR_TEIF0_MskETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_MskWWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)CAN_IER_FMPIE0_Pos (1U)RTC_ALRMBR_MNT_Pos (12U)portTASK_USES_FLOATING_POINT() FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)_ATFILE_SOURCE 1MemoryManagement_IRQnTIM_DIER_CC2IE TIM_DIER_CC2IE_MskDebugMonitor_IRQnETH_MACFFR_PAM_Pos (4U)RTC_BKP5R RTC_BKP5R_MskCAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOPCAN_F0R2_FB11 CAN_F0R2_FB11_MskEXTI0_IRQnCAN_F0R2_FB2 CAN_F0R2_FB2_MskADC_CR2_DMA ADC_CR2_DMA_MskCAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)FSMC_PCR2_PBKEN_Pos (2U)FLASH_ACR_ICEN_Pos (9U)DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_MskTIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_MskTIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)_ZN5crash15call_crash_mainEPKcmmmUART_DMA_PERIPH LL_AHB1_GRP1_PERIPH_DMA2USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETPStaticTask_t__CORE_CM3_H_DEPENDANT USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)USB_OTG_GINTSTS_MMIS_Pos (1U)USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)__glibcxx_requires_irreflexive_pred2(_First,_Last,_Pred) TIM_CALC_DTS(__TIMCLK__,__CKD__) (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))EXTI_RTSR_TR20_Pos (20U)RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)EXTI_PR_PR12_Pos (12U)UINT_FAST32_MAXCAN_F13R2_FB28_Pos (28U)RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)CAN_TDL1R_DATA1_Pos (8U)listGET_ITEM_VALUE_OF_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )operator()USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)USB_OTG_GINTMSK_PTXFEM_Pos (26U)USART_CR2_CPHA USART_CR2_CPHA_MskDMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_MskRTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)CAN_F12R1_FB25_Pos (25U)CAN_F13R2_FB14 CAN_F13R2_FB14_MskRTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)PWR_CR_PLS_LEV3 0x00000060UETH_MACA3HR_MBC_HBits15_8 0x20000000UEXTI_IMR_MR9_Pos (9U)CAN_F9R2_FB17_Pos (17U)RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_MskFSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)USB_OTG_NPTXFSA_Pos (0U)EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)CAN_FFA1R_FFA10_Pos (10U)UINT32_MAX __UINT32_MAX__CAN_TSR_ABRQ0_Pos (7U)USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_MskCAN_F5R1_FB7_Pos (7U)CAN_F4R1_FB12_Pos (12U)DCMI_CR_CM DCMI_CR_CM_MskRCC_AHB1ENR_ETHMACEN_Pos (25U)RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)xTaskNotifyAndQueryIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)RTC_WUTR_WUT RTC_WUTR_WUT_Msk__UINT32_MAX__ 0xffffffffULFLASH_OPTCR_BOR_LEV_Pos (2U)__GXX_TYPEINFO_EQUALITY_INLINE 0__cpp_lib_endian 201907LCAN_F10R2_FB15 CAN_F10R2_FB15_MskTIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)rx_reqRCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)FSMC_BTR4_DATAST FSMC_BTR4_DATAST_MskRTC_BKP3R RTC_BKP3R_MskUSB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)USB_OTG_HCCHAR_ODDFRM_Pos (29U)SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)ITM_IMCR_INTEGRATION_Msk (1UL )CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)USART_CR2_LBDIE_Pos (6U)FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACENCAN_RDL0R_DATA2_Pos (16U)CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)EXTI_EMR_MR17 EXTI_EMR_MR17_MskUSART_DR_DR USART_DR_DR_MskLL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)CAN_F2R1_FB8_Pos (8U)FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)SMCRETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_MskRCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_MskUSB_OTG_NPTXFD USB_OTG_NPTXFD_MskCAN_F1R2_FB28_Pos (28U)CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)ADC_IRQnCAN_F3R1_FB22 CAN_F3R1_FB22_MskEXTI_PR_PR4_Pos (4U)CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)mblt0__INT_FAST32_WIDTH__ 32CAN_F6R1_FB22_Pos (22U)CAN_FS1R_FSC23 CAN_FS1R_FSC23_MskUSB_OTG_HCINTMSK_STALLM_Pos (3U)CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_MskADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)CAN_F6R2_FB29 CAN_F6R2_FB29_MskLIST_H pdFREERTOS_ERRNO_ESPIPE 29GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)CAN_F3R2_FB5_Pos (5U)PWR_CSR_BRR_Pos (3U)SPI_CR2_RXDMAEN_Pos (0U)RCC_APB2LPENR_ADC3LPEN_Pos (10U)CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)FSMC_PMEM3_MEMHOLD3_Pos (16U)__UNALIGNED_UINT32_WRITE(addr,val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_MskFSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_MskRCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_MskUSB_OTG_HS_MAX_OUT_ENDPOINTS 6UI2C_SR1_RXNE_Pos (6U)__INT8_TYPE__ signed charCAN_F6R1_FB16_Pos (16U)ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)_REENT_EMERGENCY_SIZE 25EXTI_FTSR_TR19_Pos (19U)USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)CAN_FA1R_FACT25 CAN_FA1R_FACT25_MskRTC_PRER_PREDIV_S_Msk (0x1FFFUL << RTC_PRER_PREDIV_S_Pos)FSMC_PCR2_TAR FSMC_PCR2_TAR_MskUSB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_MskADC_SMPR2_SMP6_Pos (18U)CAN_F12R2_FB18 CAN_F12R2_FB18_MskADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk__ARMEL__ 1CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)ETH_MACCR_RD_Pos (9U)DMA_SxCR_MINC_Pos (10U)RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_MsktraceTASK_SUSPEND(pxTaskToSuspend) CAN2_TX_IRQnGPIO_OTYPER_OT2 0x00000004UGPIO_BSRR_BR5 0x00200000UUSB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)CAN_F8R2_FB15 CAN_F8R2_FB15_MskINTMAX_MIN (-INTMAX_MAX - 1)RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)CAN_FS1R_FSC27_Pos (27U)FSMC_BWTR1_BUSTURN_Pos (16U)__STM32F2xx_LL_DMA_H CAN_F1R2_FB10 CAN_F1R2_FB10_MskCAN_F9R1_FB5_Pos (5U)RCC_AHB1ENR_GPIODEN_Pos (3U)_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)TIM_SR_UIF TIM_SR_UIF_MskADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)SYSCFG_EXTICR3_EXTI8_PD 0x00000003URTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)__STDC__ 1CAN_F12R2_FB17 CAN_F12R2_FB17_MskETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)CAN_F8R1_FB26_Pos (26U)EXTI_SWIER_SWIER22_Pos (22U)SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)TIM7_IRQnIS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))RTC_BKP9R RTC_BKP9R_Msk_MOVE_H 1DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1DMA_HISR_TEIF7_Pos (25U)RCC_CFGR_PPRE1_DIV1 0x00000000UEXTI_EMR_MR18 EXTI_EMR_MR18_MskUSB_OTG_HCFG_FSLSPCS_Pos (0U)SDIO_IRQnUSB_OTG_PCGCCTL_PHYSUSP_Pos (4U)SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_MskETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)CAN_MCR_DBF_Pos (16U)USB_OTG_DIEPMSK_TOM_Pos (3U)ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)SDIO_MASK_DCRCFAILIE_Pos (1U)__WFI() __ASM volatile ("wfi")_PSTL_CPP14_VARIABLE_TEMPLATES_PRESENT (!__INTEL_COMPILER || __INTEL_COMPILER >= 1700) && (_MSC_FULL_VER >= 190023918 || __cplusplus >= 201402L)USART_CR1_WAKE USART_CR1_WAKE_MskTIM_BDTR_OSSI TIM_BDTR_OSSI_MskFSMC_BTR2_DATAST_Pos (8U)CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_MskCAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)EXTI_SWIER_SWIER7_Pos (7U)GPIO_BSRR_BS11 0x00000800URCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_MskGPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_MskCAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)CAN_F10R1_FB21 CAN_F10R1_FB21_MskCAN_MSR_TXM CAN_MSR_TXM_MskSCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)RTC_PRER_PREDIV_A_Pos (16U)CAN_F7R2_FB12_Pos (12U)DMA_HIFCR_CTEIF4_Pos (3U)TSDRCAN_F13R1_FB15 CAN_F13R1_FB15_MskCFGPULLETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)CAN_F11R1_FB13_Pos (13U)ETH_MACPMTCSR_MPR_Pos (5U)GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6))CAN_FA1R_FACT2_Pos (2U)USB_OTG_DOEPMSK_OTEPDM_Pos (4U)indentDMA_HIFCR_CHTIF4_Pos (4U)LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIRlistIS_CONTAINED_WITHIN(pxList,pxListItem) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)ETH_DMATDLAR_STL_Pos (0U)_PSTL_PRAGMA(x) _Pragma(#x)__FRACT_MAX__ 0X7FFFP-15RGPIO_MODER_MODE2_1 0x00000020U___int_wchar_t_h RCC_APB2RSTR_USART6RST_Pos (5U)pdFREERTOS_ERRNO_EBUSY 16LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS_GLIBCXX_HAVE_COSF 1ETH_DMABMR_RTPR_4_1 0x0000C000U__UFRACT_FBIT__ 16USB_OTG_GUSBCFG_ULPIAR_Pos (18U)USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)ISPRADC_JSQR_JSQ4 ADC_JSQR_JSQ4_MskFSMC_BCR4_MTYP FSMC_BCR4_MTYP_MskCAN_F4R1_FB21 CAN_F4R1_FB21_MskUSB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)__nosanitizememory GPIO_ODR_ODR_9 GPIO_ODR_OD9USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_MskDMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)CAN_F9R2_FB22_Pos (22U)EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_MskPOSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)RCC_BDCR_LSERDY RCC_BDCR_LSERDY_MskCAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)ITM_TCR_DWTENA_Pos 3URCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_MskRTC_ALRMAR_PM RTC_ALRMAR_PM_MskETH_MACFFR_HM_Pos (2U)SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)EXTI_PR_PR1 EXTI_PR_PR1_MskCAN_F12R1_FB10 CAN_F12R1_FB10_MskADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)RTC_DR_MT_Pos (12U)ETH_MACA2HR_MBC ETH_MACA2HR_MBC_MskFSMC_BCR4_MTYP_Pos (2U)ADC_SR_STRT ADC_SR_STRT_MskIWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)xTaskNotifyWaitIndexed(uxIndexToWaitOn,ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )TIM_SR_CC3OF_Pos (11U)ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)__ARM_ARCH_ISA_THUMB 2CAN_F4R2_FB6_Pos (6U)SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)CAN_F13R2_FB19_Pos (19U)GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0__asserts_exclusive(...) __lock_annotate(assert_exclusive_lock(__VA_ARGS__))USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)tskMPU_REGION_READ_ONLY ( 1UL << 0UL )_GLIBCXX_USE_C99_FENV_TR1 1CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)FSMC_BCR4_CBURSTRW_Pos (19U)CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)CAN_F13R1_FB17_Pos (17U)FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk__UINT16_MAX__ 0xffffCAN_BTR_LBKM_Pos (30U)CAN_F7R1_FB17 CAN_F7R1_FB17_MskDCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_MskRTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)CAN_FA1R_FACT2 CAN_FA1R_FACT2_MskCAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_MskCAN_F0R1_FB12 CAN_F0R1_FB12_MskCAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)GPIO_AFRL_AFSEL3_0 0x00001000UFSMC_BTR4_ACCMOD_Pos (28U)DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_MskRTC_ALRMAR_MNT RTC_ALRMAR_MNT_MskCAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)RTC_CR_SUB1H_Pos (17U)CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)CAN_F3R2_FB19 CAN_F3R2_FB19_MskADC_CSR_AWD2 ADC_CSR_AWD2_MskGPIO_AFRH_AFSEL11_0 0x00001000UCAN_RDH0R_DATA4 CAN_RDH0R_DATA4_MskCAN_F7R2_FB5_Pos (5U)GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_MskCAN_F11R2_FB0 CAN_F11R2_FB0_MskRCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)CAN_F12R2_FB14_Pos (14U)SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)_ZNK3srv8Servicer11PendRequest18CalibrationRequestcvbEvEXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)CAN_TSR_TERR0_Pos (3U)USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_MskETH_MACA2HR_MBC_LBits23_16 0x04000000U__USACCUM_MAX__ 0XFFFFP-8UHK_SYS_CDEFS_H_ CAN_F1R1_FB23_Pos (23U)DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_MskCAN_TI2R_RTR_Pos (1U)CAN_F0R2_FB0_Pos (0U)CAN_RI0R_EXID_Pos (3U)__USACCUM_EPSILON__ 0x1P-8UHKADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)ETH_DMASR_RPS_Stopped 0x00000000UADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)srvcsrvdCAN_F9R2_FB3 CAN_F9R2_FB3_Msk__STM32F2xx_H FSMC_BCR4_FACCEN_Pos (6U)GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0__FLT64_HAS_QUIET_NAN__ 1USB_OTG_DOEPCTL_USBAEP_Pos (15U)SCB_CPUID_PARTNO_Pos 4UsrvpGPIO_IDR_IDR_10 GPIO_IDR_ID10USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)SPI_SR_CHSIDE SPI_SR_CHSIDE_MskLL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAENGPIO_PUPDR_PUPD10 0x00300000USYSCFG_EXTICR1_EXTI3_Pos (12U)CAN_F2R1_FB20_Pos (20U)ETH_MACCR_RE_Pos (2U)I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk__nonnull_all __attribute__((__nonnull__))LL_GPIO_PIN_8 GPIO_BSRR_BS_8FSMC_PCR3_PBKEN_Pos (2U)RCC_CFGR_MCO2PRE_Pos (27U)_RAND48_ADD (0x000b)CAN_F6R1_FB30 CAN_F6R1_FB30_MskCAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_MskRCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_MskCAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_MskUSB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 )GPIO_PUPDR_PUPD7_0 0x00004000UGPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)CAN_RDL1R_DATA1_Pos (8U)USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)ARM_MPU_AP_PRO 5UTIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)configINITIAL_TICK_COUNT 0USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)__INT_FAST8_MAX__ 0x7fffffff__UDQ_IBIT__ 0FLASH_CR_SNB_Pos (3U)FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)IWDG_PR_PR_Pos (0U)EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_MskRCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1configUSE_TRACE_FACILITY 0CAN_F3R1_FB27_Pos (27U)MPU_CTRL_PRIVDEFENA_Pos 2USDIO_STA_SDIOIT_Pos (22U)FLASH_OPTCR_nWRP_Pos (16U)USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk__glibcxx_max_digits10traceSTREAM_BUFFER_CREATE(pxStreamBuffer,xIsMessageBuffer) __guarded_by(x) __lock_annotate(guarded_by(x))SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)__strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))CAN_F11R2_FB1 CAN_F11R2_FB1_MskTIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)CAN_F0R1_FB9_Pos (9U)8SCB_TypeSYSCFG_EXTICR4_EXTI14_Pos (8U)drawCAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)SYSCFG_EXTICR3_EXTI10_Pos (8U)CAN_F7R2_FB7 CAN_F7R2_FB7_MskRTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0INT_LEAST64_MIN__attribute_format_strfmon__(a,b) USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_MskDMA_HISR_DMEIF5 DMA_HISR_DMEIF5_MskSDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_MskGPIO_OSPEEDR_OSPEED12 0x03000000UI2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk__need_ptrdiff_tGPIO_MODER_MODER6 GPIO_MODER_MODER6_MskCAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)TIM_CCMR1_OC1FE_Pos (2U)GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_MskCAN_TDL1R_DATA2 CAN_TDL1R_DATA2_MskADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)CAN_F6R1_FB8 CAN_F6R1_FB8_MskRCC_APB1RSTR_UART5RST_Pos (20U)CAN_F4R1_FB22_Pos (22U)__STM32F2xx_CMSIS_VERSION_SUB2 (0x05U)ETH_DMAIER_ROIE_Pos (4U)CAN_F2R2_FB13_Pos (13U)SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)ETH_MACCR_DC_Pos (4U)CAN_F8R1_FB16 CAN_F8R1_FB16_MskGPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)__UINT_FAST8_TYPE__ unsigned intDWT_BASE (0xE0001000UL)ADC_CR1_JEOCIE_Pos (7U)FLASH_ACR_DCEN FLASH_ACR_DCEN_MskTIM_CCMR1_CC2S TIM_CCMR1_CC2S_MskRCC_AHB1ENR_GPIOAEN_Pos (0U)TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_MskCAN_F7R1_FB18_Pos (18U)RCC_APB2LPENR_ADC1LPEN_Pos (8U)GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14USB_OTG_HCINT_XFRC_Pos (0U)CAN_F8R1_FB3_Pos (3U)SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_MskFSMC_BCR3_CBURSTRW_Pos (19U)RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_MsktraceTASK_PRIORITY_INHERIT(pxTCBOfMutexHolder,uxInheritedPriority) ETH_DMASR_FBES ETH_DMASR_FBES_MskGPIO_PUPDR_PUPD5_1 0x00000800UDMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)__ARM_FEATURE_FP16_VECTOR_ARITHMETICUSB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_MskADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)GPIO_OSPEEDR_OSPEED14_0 0x10000000USDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)ETH_DMAMFBOCR_MFC_Pos (0U)CAN_F11R1_FB2_Pos (2U)RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)CAN_FS1R_FSC0 CAN_FS1R_FSC0_MskTPI_ACPR_PRESCALER_Pos 0UI2C_CR1_STOP I2C_CR1_STOP_MskCAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)CAN_F7R1_FB6_Pos (6U)CAN_FS1R_FSC7_Pos (7U)INCLUDE_xTimerPendFunctionCall 0CAN_F0R2_FB30 CAN_F0R2_FB30_MskTIM_CCER_CC4P TIM_CCER_CC4P_MskCAN_F4R2_FB23_Pos (23U)ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)SRAM2_BB_BASE 0x22380000ULTPI_ACPR_PRESCALER_Msk (0x1FFFUL )FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)CAN_F10R1_FB17_Pos (17U)USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk__USAT(ARG1,ARG2) __extension__ ({ uint32_t __RES, __ARG1 = (ARG1); __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); __RES; })SYSCFG_CMPCR_CMP_PD_Pos (0U)ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)RTC_BKP19R_Pos (0U)CAN_TSR_LOW CAN_TSR_LOW_MskRCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk_GLIBCXX98_USE_C99_STDLIB 1RCC_CFGR_PPRE1_DIV8 0x00001800UtraceTASK_NOTIFY_TAKE_BLOCK(uxIndexToWait) ETH_MACSR_PMTS ETH_MACSR_PMTS_MskDBGMCU_CR_DBG_STANDBY_Pos (2U)ADC_CR2_CONT_Pos (1U)_GLIBCXX_PREDEFINED_OPS_H 1CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)USB_OTG_GOTGINT_DBCDNE_Pos (19U)ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)CAN_F4R1_FB7 CAN_F4R1_FB7_MskCAN_FFA1R_FFA12 CAN_FFA1R_FFA12_MskTIM_DIER_TDE_Pos (14U)USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_MsktnameEXTI_FTSR_TR21_Pos (21U)GPIO_BSRR_BS_1 GPIO_BSRR_BS1SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)CAN_F9R1_FB11_Pos (11U)tmrTIMER_CALLBACK TimerCallbackFunction_tSDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_MskMPU_RBAR_VALID_Pos 4U_GLIBCXX_INVOKE_H 1CAN_F9R2_FB21 CAN_F9R2_FB21_MskDMA2_Stream2_IRQn__USFRACT_MIN__ 0.0UHRUSB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_MskEXTI_EMR_EM8 EXTI_EMR_MR8CAN_F3R2_FB26 CAN_F3R2_FB26_MskFSMC_BCR1_MTYP FSMC_BCR1_MTYP_MskCAN_F12R1_FB27_Pos (27U)FSMC_PATT2_ATTHIZ2_Pos (24U)LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_MskGPIO_BSRR_BS9 0x00000200UCAN_IER_FOVIE0 CAN_IER_FOVIE0_MskCAN_F0R1_FB0_Pos (0U)RTC_BKP11R RTC_BKP11R_MskLL_SYSTICK_DisableIT_REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)CAN_F13R2_FB9_Pos (9U)CAN_F3R1_FB9 CAN_F3R1_FB9_MskCAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)CAN_F2R2_FB9 CAN_F2R2_FB9_MskCAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)CAN_FM1R_FBM4 CAN_FM1R_FBM4_MskGPIO_ODR_ODR_5 GPIO_ODR_OD5CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)CAN_F7R1_FB29 CAN_F7R1_FB29_MskPWR_CSR_PVDO_Pos (2U)RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)USB_OTG_GINTSTS_WKUINT_Pos (31U)ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)__UACCUM_IBIT__ 16CAN_F11R1_FB3 CAN_F11R1_FB3_MskETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_MskDMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_MskADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)CAN_F6R1_FB0 CAN_F6R1_FB0_MskRCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)_GLIBCXX_LT_OBJDIR ".libs/"CAN_F5R2_FB0 CAN_F5R2_FB0_MskETH_MACCR_IFG_56Bit 0x000A0000UCAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_MskCAN_F5R2_FB12 CAN_F5R2_FB12_Msk__TQ_IBIT__ 0CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_MskGPIO_PUPDR_PUPD4_0 0x00000100U__CMSIS_GCC_OUT_REG(r) "=r" (r)SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_MskSSCGRLL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOPGPIO_MODER_MODER8 GPIO_MODER_MODER8_MskNVIC_SystemReset __NVIC_SystemReset__have_long32 1ETH_DMABMR_RDP_1Beat 0x00020000UCAN_F9R1_FB5 CAN_F9R1_FB5_MskRCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_MskIS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || ((INSTANCE) == DMA1_Stream1) || ((INSTANCE) == DMA1_Stream2) || ((INSTANCE) == DMA1_Stream3) || ((INSTANCE) == DMA1_Stream4) || ((INSTANCE) == DMA1_Stream5) || ((INSTANCE) == DMA1_Stream6) || ((INSTANCE) == DMA1_Stream7) || ((INSTANCE) == DMA2_Stream0) || ((INSTANCE) == DMA2_Stream1) || ((INSTANCE) == DMA2_Stream2) || ((INSTANCE) == DMA2_Stream3) || ((INSTANCE) == DMA2_Stream4) || ((INSTANCE) == DMA2_Stream5) || ((INSTANCE) == DMA2_Stream6) || ((INSTANCE) == DMA2_Stream7))portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()GPIO_OSPEEDR_OSPEED1 0x0000000CUUSB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)CAN_F0R2_FB16_Pos (16U)CAN_FS1R_FSC_Pos (0U)GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_MskITM_TCR_ITMENA_Pos 0UETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)CAN_F0R1_FB27_Pos (27U)RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)CAN_F4R2_FB2 CAN_F4R2_FB2_MskDCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_MskRCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)CAN_F2R2_FB7_Pos (7U)LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_MskWINT_MAX __WINT_MAX__FLASH_ACR_DCEN_Pos (10U)RTC_CR_COE RTC_CR_COE_MskUSB_OTG_DIEPTXF_INEPTXSA_Pos (0U)FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)ETH_MACCR_BL_Pos (5U)ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)CAN_F11R2_FB30_Pos (30U)USART_SR_FE USART_SR_FE_MskRTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)DAC_CR_DMAEN2 DAC_CR_DMAEN2_MskSPI2_BASE (APB1PERIPH_BASE + 0x3800UL)CAN_TDL2R_DATA0_Pos (0U)ADC_SR_EOC_Pos (1U)Pin<1073873920, 6>INT8_C(c) __INT8_C(c)__CONCAT(x,y) __CONCAT1(x,y)RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)LL_TIM_ETR_FILTER_FDIV1 0x00000000U__UACCUM_MIN__ 0.0UKFSMC_BCR2_CBURSTRW_Pos (19U)TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)EXTI_IMR_MR3_Pos (3U)CAN_F5R2_FB6_Pos (6U)USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)RCC_AHB2RSTR_RNGRST_Pos (6U)GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5CAN_F5R1_FB27_Pos (27U)CAN_F11R2_FB30 CAN_F11R2_FB30_MskTPI_FFCR_EnFCont_Pos 1UIS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)CAN_F13R2_FB17_Pos (17U)ADC_CSR_JEOC2 ADC_CSR_JEOC2_MskI2C_OAR1_ADD2_Pos (2U)__DBL_HAS_QUIET_NAN__ 1SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)CAN_ESR_EPVF_Pos (1U)CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)_GLIBCXX_CONST __attribute__ ((__const__))FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)__ATOMIC_RELEASE 3CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_MskCAN_F1R2_FB30_Pos (30U)CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)__cpp_hex_float 201603LCAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)EXTI_IMR_IM19 EXTI_IMR_MR19DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_MskRCC_AHB1RSTR_GPIOCRST_Pos (2U)CAN_F11R2_FB1_Pos (1U)ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)__ACCUM_MAX__ 0X7FFFFFFFP-15KCAN_F8R1_FB23 CAN_F8R1_FB23_MskETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)__DBL_IS_IEC_60559__ 1USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_MskADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)CAN_IER_FFIE1 CAN_IER_FFIE1_MskADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)CAN_F4R2_FB25 CAN_F4R2_FB25_MskUSB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)traceTASK_NOTIFY_WAIT_BLOCK(uxIndexToWait) EXTI_PR_PR17 EXTI_PR_PR17_MskCAN_F1R2_FB23_Pos (23U)ADC_SMPR1_SMP16_Pos (18U)USART_CR3_RTSE_Pos (8U)USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)CAN_F1R1_FB2 CAN_F1R1_FB2_MskCAN_RI1R_EXID_Pos (3U)__FLT_DENORM_MIN__ 1.4012984643248171e-45FSDIO_MASK_STBITERRIE_Pos (9U)ETH_MACCR_TE_Pos (3U)FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_MskADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)__hidden __attribute__((__visibility__("hidden")))RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_MskI2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)DCMI_CR_HSPOL_Pos (6U)USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)_ZN5crash4srvd21ServicerDebugAccessor35get_debug_servicer_pending_requestsEvETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)_GLIBCXX_HAVE_ISWBLANK 1DCMI_CWSTRT_VST_Pos (16U)CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)CAN_F1R2_FB17_Pos (17U)RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)DMA_HISR_TCIF7 DMA_HISR_TCIF7_MskUSB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_MskRCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_MskCAN_F4R1_FB14 CAN_F4R1_FB14_MskLL_GPIO_PIN_9 GPIO_BSRR_BS_9CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)SDIO_MASK_TXUNDERRIE_Pos (4U)DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_MsksemBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U )CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_MskCAN_F6R1_FB14 CAN_F6R1_FB14_MskUSB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_MskGPIO_ODR_OD5 0x00000020U__NEWLIB_PATCHLEVEL__ 0CAN_F0R1_FB4 CAN_F0R1_FB4_MskCAN_F6R2_FB11 CAN_F6R2_FB11_MskUSB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_MskRCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_MskCAN_F0R2_FB16 CAN_F0R2_FB16_MskCAN_BTR_LBKM CAN_BTR_LBKM_Msk_GTHREAD_USE_MUTEX_TIMEDLOCK 1ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_MskRTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)DMA_HIFCR_CHTIF5_Pos (10U)CAN_F2R1_FB3 CAN_F2R1_FB3_Msk__ARM_ARCH 7ETH_MACMIIAR_MB ETH_MACMIIAR_MB_MskUSB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk__LDBL_DIG__ 15_GLIBCXX_HAVE_IS_CONSTANT_EVALUATED 1GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)CAN_F3R2_FB27_Pos (27U)RTC_ALRMAR_HT_Pos (20U)ADC_CR2_DMA_Pos (8U)SYSCFG_EXTICR3_EXTI11_PH 0x00007000ULL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)CAN_F4R1_FB16 CAN_F4R1_FB16_MskFSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)CAN_FA1R_FACT17 CAN_FA1R_FACT17_MskUSB_OTG_GAHBCFG_PTXFELVL_Pos (8U)ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)SDIO_CLKCR_BYPASS_Pos (10U)GPIO_AFRH_AFSEL15 0xF0000000UUSB_OTG_PCGCR_PHYSUSP_Pos (4U)CAN_FS1R_FSC16_Pos (16U)CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)CAN_F0R1_FB31 CAN_F0R1_FB31_MskFLASH_END 0x080FFFFFULFLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)DMA_HISR_FEIF7_Pos (22U)DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_MskETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6configTIMER_TASK_PRIORITY (2)EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_MskPendSV_IRQnDBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)EXTI_SWIER_SWIER11_Pos (11U)traceMALLOC(pvAddress,uiSize) DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_MsktraceQUEUE_RECEIVE_FAILED(pxQueue) _ZN5crash6Matrix4initEvMPU_RASR_B_Pos 16UEXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_MskFSMC_BCR1_CBURSTRW_Pos (19U)EXTI_IMR_IM1 EXTI_IMR_MR1USB_OTG_DOEPINT_NAK_Pos (13U)I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_MskconfigUSE_POSIX_ERRNO 0RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_MskUSB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)CoreDebug_DEMCR_VC_INTERR_Pos 9UUSB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)ADC_CCR_TSVREFE_Pos (23U)SYSCFG_EXTICR3_EXTI11_PB 0x00001000UCAN_F11R1_FB31 CAN_F11R1_FB31_MskCAN_F9R1_FB22 CAN_F9R1_FB22_MskETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)DMA_HISR_DMEIF6_Pos (18U)USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)GPIO_MODER_MODE12 0x03000000URCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_MskFSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)TIM_DIER_CC2IE_Pos (2U)CAN_F12R1_FB2_Pos (2U)TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_MskRTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)DMA_SxCR_CT DMA_SxCR_CT_MskCAN_F8R1_FB6_Pos (6U)RTC_BKP1R RTC_BKP1R_MskRCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)FSMC_BCR1_FACCEN_Pos (6U)__ULFRACT_EPSILON__ 0x1P-32ULRGPIO_AFRH_AFSEL14_2 0x04000000UconfigRUN_FREERTOS_SECURE_ONLY 0ETH_DMABMR_RDP_2Beat 0x00040000U_GLIBCXX_USE_C99_STDINT_TR1 1USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)vTaskNotifyGiveIndexedFromISR(xTaskToNotify,uxIndexToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) );USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_MskSDIO_MASK_TXDAVLIE_Pos (20U)LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)__cpp_lib_ssize 201902LRTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)RCC_CIR_PLLRDYF_Pos (4U)LL_TIM_OCPOLARITY_HIGH 0x00000000URCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk__cpp_lib_constexpr_iterator 201811LGPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1I2C_SR1_SMBALERT_Pos (15U)USB_OTG_GRXFSIZ_RXFD_Pos (0U)ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)DCMI_CR_ENABLE_Pos (14U)DMA_LISR_TEIF2_Pos (19U)TIM_SMCR_ETF_Pos (8U)CAN_F5R1_FB13 CAN_F5R1_FB13_MskLL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1ENCAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)HFSRI2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)TIM_DCR_DBA_Pos (0U)DCMI_DR_BYTE1 DCMI_DR_BYTE1_MskETH_DMASR_RPS_Waiting_Pos (17U)CAN_F10R1_FB0 CAN_F10R1_FB0_MskFSMC_PCR2_PWID FSMC_PCR2_PWID_MskUSB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)GPIO_IDR_ID9 0x00000200UEXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOPStackType_tRCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_MskCAN_F1R1_FB0_Pos (0U)listGET_END_MARKER(pxList) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_MskEXTI_PR_PR20 EXTI_PR_PR20_MsktraceTASK_NOTIFY_GIVE_FROM_ISR(uxIndexToNotify) CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)call_crash_mainRTC_TSDR_DT RTC_TSDR_DT_MskCAN_F3R1_FB7 CAN_F3R1_FB7_MskETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)INT_LEAST16_MIN (-INT_LEAST16_MAX - 1)RTC_TR_HT_Pos (20U)__ULACCUM_MIN__ 0.0ULKDAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)CAN_F4R1_FB30 CAN_F4R1_FB30_MskCoreDebug_DCRSR_REGSEL_Msk (0x1FUL )RCC_APB1ENR_TIM4EN_Pos (2U)ETH_PTPTSLUR_TSUSS_Pos (0U)ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_MskFSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_MskCAN_F10R2_FB28_Pos (28U)ITM_TCR_GTSFREQ_Pos 10U__GNUCLIKE_BUILTIN_CONSTANT_P 1LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRSTCAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)_GLIBCXX_RELEASE 13TIM_EGR_TG TIM_EGR_TG_MskDMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)USB_OTG_TX0FD_Pos (16U)~TimeRequest__STM32F2xx_LL_BUS_H GPIO_PUPDR_PUPD2_1 0x00000020UTIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)CAN_F0R2_FB8_Pos (8U)__UACCUM_EPSILON__ 0x1P-16UKFLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)GPIO_PUPDR_PUPD9 0x000C0000UUSART_CR3_DMAR_Pos (6U)USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)for_all_in_queue >SDIO_STA_TXFIFOF_Pos (16U)SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_MskCAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)SYSCFG_EXTICR4_EXTI14_PE 0x00000400UtraceCREATE_MUTEX(pxNewQueue) TIM_CR1_DIR TIM_CR1_DIR_Msk__ARM_FEATURE_PAUTHCAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)I2C_OAR1_ADD3 I2C_OAR1_ADD3_MskUINTPTR_MAX __UINTPTR_MAX__ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_MskMPU_RASR_ENABLE_Msk (1UL )FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_MskSDIO_DCTRL_RWSTART_Pos (8U)DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)RCC_SSCGR_MODPER_Pos (0U)__cpp_lib_is_nothrow_convertible 201806LSDIO_DCTRL_DTEN_Pos (0U)CAN_F3R2_FB7_Pos (7U)PORTMACRO_H CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )CAN_TSR_TXOK1 CAN_TSR_TXOK1_MskADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)DT_DELAY_1 ((uint8_t)0x7F)CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_MskUSART_CR2_CPOL_Pos (10U)DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)DMA_HIFCR_CFEIF6_Pos (16U)TPI_FIFO1_ETM_bytecount_Pos 24UFSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)CAN_F4R1_FB26 CAN_F4R1_FB26_MskLL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)CAN_F13R2_FB4 CAN_F13R2_FB4_MskRTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_MskSYSCFG_EXTICR2_EXTI4_PB 0x00000001UFSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Mskshow_backtrace_forRCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)CAN_F3R1_FB22_Pos (22U)DAC_CR_BOFF1_Pos (1U)RTC_ISR_INIT RTC_ISR_INIT_MskxTaskNotifyGive(xTaskToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )CAN_F10R1_FB26_Pos (26U)FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)__ULLACCUM_MIN__ 0.0ULLKFSMC_BWTR4_ADDSET_Pos (0U)DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)CAN_TSR_LOW0 CAN_TSR_LOW0_MskEXTI_EMR_EM19 EXTI_EMR_MR19GPIO_IDR_ID7 0x00000080URTC_CALIBR_DC_Pos (0U)GPIO_OSPEEDR_OSPEED8_0 0x00010000U__INT_LEAST32_WIDTH__ 32USB_OTG_DCFG_ERRATIM_Pos (15U)FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)GPIO_PUPDR_PUPD11 0x00C00000UGPIO_MODER_MODE4_0 0x00000100UCAN_F3R1_FB16_Pos (16U)SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_MskCAN_F0R1_FB17 CAN_F0R1_FB17_MskINT32_MAX __INT32_MAX__ADC_DR_ADC2DATA ADC_DR_ADC2DATA_MskIS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)ADC_CR1_AWDSGL_Pos (9U)CAN_RI0R_IDE CAN_RI0R_IDE_MskGPIO_MODER_MODE3_1 0x00000080UTIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)USB_OTG_HS_MAX_IN_ENDPOINTS 6U_LOCK_RECURSIVE_T _LOCK_TCAN_F10R2_FB31 CAN_F10R2_FB31_MskINT16_MAX __INT16_MAX__GPIO_MODER_MODER13 GPIO_MODER_MODER13_MskLL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1)USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)CAN_F8R1_FB15_Pos (15U)SYSCFG_EXTICR3_EXTI8_PC 0x00000002UDMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)FSMC_IRQnFSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)EXTI_IMR_IM12 EXTI_IMR_MR12EXTI_FTSR_TR18 EXTI_FTSR_TR18_MskCAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)GPIO_IDR_ID4 0x00000010UCAN_F5R2_FB31 CAN_F5R2_FB31_MskFSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)_GLIBCXX_HAVE_FABSF 1CAN_MSR_WKUI_Pos (3U)FSMC_SR3_ILS_Pos (1U)CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)CAN_F5R1_FB26_Pos (26U)DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)DMA2 ((DMA_TypeDef *) DMA2_BASE)LL_GPIO_AF_15 (0x000000FU)__HA_FBIT__ 7LL_GPIO_PIN_13 GPIO_BSRR_BS_13USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_MskCAN_F12R2_FB27 CAN_F12R2_FB27_MskFSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_MskSCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk__INT_N(TYPE) __extension__ template<> struct __is_integer { enum { __value = 1 }; typedef __true_type __type; }; __extension__ template<> struct __is_integer { enum { __value = 1 }; typedef __true_type __type; };USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_MskI2C_TRISE_TRISE I2C_TRISE_TRISE_MskCoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)IPSR_ISR_Pos 0UFSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)GPIO_IDR_IDR_14 GPIO_IDR_ID14ADC_SQR2_SQ12 ADC_SQR2_SQ12_MskCAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_MskCAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP__THROW TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MISUSB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)LL_DMA_CHANNEL_0 0x00000000ULL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK)RCC_APB1LPENR_TIM12LPEN_Pos (6U)CAN_F5R1_FB20 CAN_F5R1_FB20_MskFSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)FSMC_PCR2_TCLR FSMC_PCR2_TCLR_MskADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)timer_finishedRTC_CR_BKP RTC_CR_BKP_MsktaskENTER_CRITICAL() portENTER_CRITICAL()FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)CAN_F13R2_FB3 CAN_F13R2_FB3_MskRCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)CoreDebug_DHCSR_C_HALT_Pos 1UFSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_MskRCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)CAN_F8R2_FB27 CAN_F8R2_FB27_MskGPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0ETH_MACDBGR_MMRPEA_Pos (0U)CAN_F1R2_FB22 CAN_F1R2_FB22_MskCAN_F4R2_FB12_Pos (12U)ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)xSemaphoreGiveFromISR(xSemaphore,pxHigherPriorityTaskWoken) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_MskUSB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)CAN_F9R2_FB16 CAN_F9R2_FB16_MskUSB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)GPIO_LCKR_LCK11_Pos (11U)FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_MskFSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)GPIO_ODR_ODR_11 GPIO_ODR_OD11RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)CAN_F5R1_FB31_Pos (31U)SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)pdFREERTOS_ERRNO_EAGAIN 11USB_OTG_GUSBCFG_TSDPS_Pos (22U)OTG_HS_WKUP_IRQnSYSCFG_EXTICR3_EXTI10_PH 0x00000700UADC_JDR2_JDATA_Pos (0U)__FLT_MIN_EXP__ (-125)INT_LEAST32_MINETH_MACCR_FES_Pos (14U)DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)ADC_CR1_JAWDEN_Pos (22U)CAN_F3R1_FB8_Pos (8U)RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_MskETH_MACA1HR_MBC_HBits15_8 0x20000000USDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_MskETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk__cpp_char8_t 202207LEXTI_EMR_MR22_Pos (22U)DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_MskCAN_FA1R_FACT5_Pos (5U)__need_wint_t SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)pdFREERTOS_ERRNO_EWOULDBLOCK 11CAN_F7R1_FB9 CAN_F7R1_FB9_MskCAN_F1R1_FB11 CAN_F1R1_FB11_MskFSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)CAN_F6R2_FB1_Pos (1U)RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_MskADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)CAN_F6R2_FB22_Pos (22U)taskYIELD() portYIELD()CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)FSMC_SR4_IREN FSMC_SR4_IREN_MskCAN_F11R2_FB17 CAN_F11R2_FB17_Msk__ARM_FEATURE_BF16_SCALAR_ARITHMETICETH_MACFCR_ZQPD_Pos (7U)ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)CAN_F10R1_FB23_Pos (23U)CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)SPI2_IRQnCAN_F10R1_FB3_Pos (3U)DMA_SxCR_EN_Pos (0U)CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)CAN_F6R2_FB16 CAN_F6R2_FB16_Msk__BSD_VISIBLE 1__DBL_MAX__ double(1.7976931348623157e+308L)ETH_MACMIIAR_MB_Pos (0U)_ZN5crash1yEFSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)CAN_F6R1_FB7_Pos (7U)11RCC_TypeDefLL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOENUSB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_MskRCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)CAN_F9R2_FB0 CAN_F9R2_FB0_MskUSB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)ADC_CR1_EOCIE ADC_CR1_EOCIE_MsktracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend,pvParameter1,ulParameter2,ret) TIM3_IRQnUSB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)FSMC_PCR3_TAR_Pos (13U)CAN_F1R1_FB19_Pos (19U)RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)configUSE_TICK_HOOK 0FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)CAN_MCR_INRQ_Pos (0U)DAC_DHR8R1_DACC1DHR_Pos (0U)configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 3OTG_FS_IRQnUSB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)TIM1 ((TIM_TypeDef *) TIM1_BASE)MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)RTC_TAFCR_TAMP1E_Pos (0U)CAN_F7R1_FB14_Pos (14U)FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_MskCAN_F10R2_FB12 CAN_F10R2_FB12_MskRCC_APB2LPENR_TIM1LPEN_Pos (0U)FSMC_BCR2_MWID FSMC_BCR2_MWID_MskDCMI_CWSTRT_VST DCMI_CWSTRT_VST_MskFLASH_OPTCR_nWRP_9 (0x200UL << FLASH_OPTCR_nWRP_Pos)CAN_F8R2_FB2 CAN_F8R2_FB2_MskCAN_F6R1_FB2 CAN_F6R1_FB2_MskEXTI_IMR_MR19_Pos (19U)__FLT32_HAS_QUIET_NAN__ 1I2C_DR_DR_Pos (0U)LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000UFLASH_CR_LOCK_Pos (31U)EXTI_IMR_MR1_Pos (1U)SYSCFG_EXTICR1_EXTI1_PC 0x00000020U_PSTL_UDR_PRESENT 1FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)_PSTL_CONFIG_H CAN_F6R1_FB17 CAN_F6R1_FB17_MskEXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_MskCAN_F8R2_FB26_Pos (26U)xSTATIC_TCB__arg_type_tag(arg_kind,arg_idx,type_tag_idx) FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2)CAN_F0R1_FB16_Pos (16U)traceEVENT_GROUP_SYNC_END(xEventGroup,uxBitsToSet,uxBitsToWaitFor,xTimeoutOccurred) ( void ) xTimeoutOccurred__STM32F2xx_CMSIS_VERSION_MAIN (0x02U)FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)WWDG_CFR_EWI WWDG_CFR_EWI_MskUSB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0RTC_ALRMBR_ST_Pos (4U)TIM_SMCR_SMS_Pos (0U)CAN_FS1R_FSC20 CAN_FS1R_FSC20_MskETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)INTPTR_MINCAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)_REENT_CHECK_SIGNAL_BUF(ptr) USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)WWDG_CFR_W2 WWDG_CFR_W_2GPIO_BSRR_BS_5 GPIO_BSRR_BS5CAN_F2R2_FB17_Pos (17U)HIFCRCAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)_GLIBCXX_HAVE_DECL_STRNLEN 1DMA_HIFCR_CFEIF4_Pos (0U)TIM1_UP_TIM10_IRQnCAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)_REENT_INIT_RESERVED_6_7 CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)CAN_F9R2_FB26 CAN_F9R2_FB26_MskRTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)APB1ENRFSMC_SR3_ILS FSMC_SR3_ILS_Msk__VFP_FP__ 1EXTI_EMR_MR3 EXTI_EMR_MR3_MskFLASH_OPTCR_nWRP_10 (0x400UL << FLASH_OPTCR_nWRP_Pos)RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_MskCAN_F2R1_FB26_Pos (26U)DCMI_ESUR_LSU DCMI_ESUR_LSU_MskFSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)__SIG_ATOMIC_TYPE__ intCAN_F11R2_FB13_Pos (13U)ETH_DMAIER_ROIE ETH_DMAIER_ROIE_MskGPIO_BSRR_BS_9 GPIO_BSRR_BS9LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFENLL_TIM_SR_CC3OF TIM_SR_CC3OFFSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_MskGPIO_PUPDR_PUPD7 0x0000C000UAPB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk_GLIBCXX_USE_C99_COMPLEX _GLIBCXX11_USE_C99_COMPLEXEXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)rebootGPIO_AFRL_AFSEL2_3 0x00000800USPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_MskCAN_F1R2_FB8_Pos (8U)_ZN5crash4rtos15is_rtos_runningEvRCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_MskCAN_F9R1_FB15 CAN_F9R1_FB15_MskCAN_F5R1_FB2 CAN_F5R1_FB2_MskCAN_FM1R_FBM26_Pos (26U)CAN_F4R2_FB2_Pos (2U)CAN_F2R1_FB10 CAN_F2R1_FB10_MskCAN_F11R1_FB23 CAN_F11R1_FB23_MskGPIOA ((GPIO_TypeDef *) GPIOA_BASE)I2C2 ((I2C_TypeDef *) I2C2_BASE)__FLT_DECIMAL_DIG__ 9_GLIBCXX_DEBUG_MACRO_SWITCH_H 1_GLIBCXX_USE_FSEEKO_FTELLO 1xPSR_T_Msk (1UL << xPSR_T_Pos)ispressedGPIO_AFRH_AFSEL8_0 0x00000001U__STDC_UTF_16__ 1CAN_F5R2_FB17 CAN_F5R2_FB17_MskETH_MACA2HR_MBC_LBits7_0 0x01000000UCAN_F1R2_FB12_Pos (12U)FLASH_OPTCR_nRST_STOP_Pos (6U)CAN_F13R2_FB23_Pos (23U)LL_GPIO_AF_12 (0x000000CU)USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)CAN_F9R1_FB31 CAN_F9R1_FB31_MskUSB_OTG_GINTMSK_NPTXFEM_Pos (5U)__PTRDIFF_MAX__ 0x7fffffffUSART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)ETH_MACCR_ROD_Pos (13U)USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)CAN_F5R1_FB9_Pos (9U)CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)RTC_BKP5R_Pos (0U)FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOPTPI_BASE (0xE0040000UL)CAN_F11R2_FB7 CAN_F11R2_FB7_MskCAN_F4R1_FB4 CAN_F4R1_FB4_MskETH_DMACHRDR_HRDAP_Pos (0U)ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)pdFREERTOS_ERRNO_EUNATCH 42CAN_F3R2_FB4 CAN_F3R2_FB4_Msk_GLIBCXX_RANGE_ACCESS_H 1TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)GPIOF ((GPIO_TypeDef *) GPIOF_BASE)RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_MskDMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)ETH_DMAIER_NISE ETH_DMAIER_NISE_MskFSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)__ARM_FEATURE_COPROCGPIO_OSPEEDR_OSPEED4 0x00000300UTIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)CAN_BTR_TS2 CAN_BTR_TS2_MskFSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_MskTIM_DIER_TIE_Pos (6U)INT8_MIN (-INT8_MAX - 1)FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UGPIO_BSRR_BS7 0x00000080UDMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk_PSTL_PRAGMA_SIMD_REDUCTION(PRM) _PSTL_PRAGMA(omp simd reduction(PRM))TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)CAN_F13R1_FB12 CAN_F13R1_FB12_MskFSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)__GCC_IEC_559 0SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)AxisCalibrationFSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)ETH_DMASR_EBS_DataTransfTx_Pos (23U)USART_CR1_SBK USART_CR1_SBK_MskDMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)CAN_F2R2_FB6 CAN_F2R2_FB6_MskDMA_HISR_TCIF7_Pos (27U)GPIO_IDR_IDR_6 GPIO_IDR_ID6RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_MskADC_SQR1_SQ13 ADC_SQR1_SQ13_MskETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)ETH_PTP_BASE (ETH_BASE + 0x0700UL)UART_GPIO_PERIPH LL_AHB1_GRP1_PERIPH_GPIOGTIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)CAN_F3R2_FB16_Pos (16U)ETH_MACIMR_PMTIM_Pos (3U)ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounterGPIO_OSPEEDR_OSPEED12_1 0x02000000UCAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)EXTI_FTSR_TR20_Pos (20U)ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)USB_OTG_HCCHAR_EPTYP_Pos (18U)GPIO_BSRR_BS4 0x00000010U_GLIBCXX_HAVE_FENV_H 1EXTI_RTSR_TR18 EXTI_RTSR_TR18_MskCAN_F8R1_FB28 CAN_F8R1_FB28_MskGPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)CAN_F1R1_FB23 CAN_F1R1_FB23_MskRCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_MskUSB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk_PSTL_STRING_AUX(x) #x__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRDBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)CAN_F6R1_FB11_Pos (11U)FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)EXTI_FTSR_TR14_Pos (14U)TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)CAN_F5R2_FB26_Pos (26U)CAN_F5R2_FB13_Pos (13U)FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)_ATEXIT_SIZE 32CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)GPIO_OTYPER_OT15 0x00008000UFSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)TIM_OR_TI4_RMP_Pos (6U)CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)CAN_FM1R_FBM16 CAN_FM1R_FBM16_MskI2C_CR1_ENGC I2C_CR1_ENGC_MskRCC_AHB1RSTR_GPIOARST_Pos (0U)CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)__glibcxx_requires_valid_range(_First,_Last) SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)CAN_FS1R_FSC22_Pos (22U)__LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)RCC_BDCR_RTCEN_Pos (15U)TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)SDIO_ICR_CMDRENDC_Pos (6U)USB_OTG_HFNUM_FRNUM_Pos (0U)ETH_MMCRIR_RGUFS_Pos (17U)CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)GPIO_OSPEEDR_OSPEED9 0x000C0000UETH_MACDBGR_MTFCS_Pos (17U)PWR_CSR_WUF PWR_CSR_WUF_MskTIM_CCMR1_OC2M_Pos (12U)RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)CAN_F8R1_FB21_Pos (21U)RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6))CAN_F6R1_FB11 CAN_F6R1_FB11_MskCAN_F1R1_FB9_Pos (9U)RCC_CFGR_MCO1_Pos (21U)USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_MskETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)GPIO_OSPEEDR_OSPEED15_1 0x80000000UDMA_LISR_FEIF1 DMA_LISR_FEIF1_MskxSTATIC_QUEUE__cpp_constexpr_dynamic_alloc 201907LRCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_MskDCMI_CR_PCKPOL_Pos (5U)ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)DMA_LISR_FEIF2_Pos (16U)CAN_F0R2_FB29_Pos (29U)I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk_PSTL_VERSION 12000TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEENUSB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)I2C_CR1_PEC I2C_CR1_PEC_MskETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)CAN_F4R1_FB8_Pos (8U)TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)SDIO_FIFO_FIFODATA_Pos (0U)StaticQueue_tCAN1 ((CAN_TypeDef *) CAN1_BASE)GPIO_LCKR_LCK5_Pos (5U)SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_MskWWDG_CR_T5 WWDG_CR_T_5GPIO_PUPDR_PUPD9_1 0x00080000UportTASK_FUNCTION_PROTO(vFunction,pvParameters) void vFunction( void * pvParameters )NVIC_GetPriority __NVIC_GetPriorityFSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)EXTI_PR_PR14 EXTI_PR_PR14_MskUSART_CR3_NACK_Pos (4U)FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)__GNU_VISIBLE 0__THUMBEL__ 1CAN_F10R2_FB23_Pos (23U)SPI_SR_TXE_Pos (1U)ETH_DMAOMR_TTC_32Bytes 0x00014000UETH_MACA1HR_MBC_LBits23_16 0x04000000UUSB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_MskGPIO_OTYPER_OT4 0x00000010USPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)RTC_WKUP_IRQnCAN_TI2R_EXID CAN_TI2R_EXID_MskCAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)SDIO_STA_TXACT_Pos (12U)INCLUDE_xTaskResumeFromISR 1SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)CAN_F5R2_FB24 CAN_F5R2_FB24_MskCAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)__GCC_ASM_FLAG_OUTPUTS__ 1IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2FSMC_BTR4_CLKDIV_Pos (20U)CAN_FA1R_FACT23 CAN_FA1R_FACT23_MskADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)__ARM_FEATURE_CMSEDMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)GPIO_OSPEEDR_OSPEED4_1 0x00000200UDCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_MskCAN_F10R2_FB17_Pos (17U)TIM_SR_UIF_Pos (0U)RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)IS_TIM_CCXN_INSTANCE(INSTANCE,CHANNEL) ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))) || (((INSTANCE) == TIM8) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))))PWR_CR_FPDS_Pos (9U)CAN_F12R2_FB19 CAN_F12R2_FB19_MskCAN_F9R2_FB8_Pos (8U)rtosFSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)CAN_F9R1_FB27 CAN_F9R1_FB27_MskDMA_LISR_TCIF0_Pos (5U)USB_OTG_GUSBCFG_PTCI_Pos (24U)_GLIBCXX_CONCEPTS 1CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)FSMC_BWTR4_ADDHLD_Pos (4U)_PSTL_CPP17_EXECUTION_POLICIES_PRESENT (_MSC_VER >= 1912)SDIO_STA_DTIMEOUT_Pos (3U)GPIO_AFRH_AFSEL8 0x0000000FURCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_MskETH_MACCR_CSD ETH_MACCR_CSD_MskUSB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_MskDAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_MskGPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)DMA_SxCR_DBM_Pos (18U)CAN_F0R1_FB14_Pos (14U)CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_MskUSART_CR2_LBCL USART_CR2_LBCL_MskETH_PTPTSAR_TSA_Pos (0U)CAN_F9R2_FB11_Pos (11U)FLASH_OPTCR_nWRP_1 (0x002UL << FLASH_OPTCR_nWRP_Pos)ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)ESP_USART USART6CAN_F7R2_FB10 CAN_F7R2_FB10_MskCAN_F1R2_FB15 CAN_F1R2_FB15_MskADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_MskCAN_F12R2_FB27_Pos (27U)TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)__FLT32X_DENORM_MIN__ 4.9406564584124654e-324F32xCAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)CAN_FFA1R_FFA4_Pos (4U)RTC_ALRMAR_MSK3_Pos (23U)__attribute_pure__ SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_MskIS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))RESERVED6ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_MskETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)_GLIBCXX_HAVE_STRING_H 1CAN_F5R1_FB18 CAN_F5R1_FB18_MskCAN_F0R2_FB2_Pos (2U)DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)USART_CR2_CLKEN USART_CR2_CLKEN_MskEXTI_EMR_MR20_Pos (20U)CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_MskLL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_MskCAN_F3R1_FB11_Pos (11U)CAN_BTR_TS1_Pos (16U)USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)LL_DMA_EnableIT_TCFSMC_BCR1_WREN_Pos (12U)__Vendor_SysTickConfig 0UDMA_LIFCR_CTEIF2_Pos (19U)SPI_I2SCFGR_CKPOL_Pos (3U)RCC_CFGR_HPRE_Pos (4U)CAN_F1R1_FB30 CAN_F1R1_FB30_MskCAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)__cpp_lib_nonmember_container_access 201411L_GLIBCXX_USE_GETTIMEOFDAY 1traceTASK_PRIORITY_DISINHERIT(pxTCBOfMutexHolder,uxOriginalPriority) USB_OTG_DIEPMSK_BIM_Pos (9U)CAN_RI1R_IDE_Pos (2U)TIM_SR_CC4OF TIM_SR_CC4OF_MskCAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)CAN_F9R1_FB22_Pos (22U)SCnSCB_ACTLR_DISMCYCINT_Pos 0UDMA_SxM0AR_M0A DMA_SxM0AR_M0A_MskRTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)SPI_SR_BSY SPI_SR_BSY_MskSDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)TIM_CCMR1_OC2CE_Pos (15U)__BIGGEST_ALIGNMENT__ 8ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_MskADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)pcTail_GLIBCXX_USE_C99 1USB_OTG_GCCFG_VBUSBSEN_Pos (19U)LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5ENRCC_CFGR_PPRE1_DIV4 0x00001400UCAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)SYSCFG_EXTICR4_EXTI14_PG 0x00000600UUSB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_MskCAN_ESR_TEC CAN_ESR_TEC_MskETH_DMASR_TJTS_Pos (3U)TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)WWDG_SR_EWIF WWDG_SR_EWIF_MskCAN_F5R1_FB21_Pos (21U)ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_MskSDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_MskUSB_OTG_HPTXFSIZ_PTXSA_Pos (0U)traceGIVE_MUTEX_RECURSIVE_FAILED(pxMutex) RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_MskRCC_CFGR_SW_Pos (0U)CAN_F12R1_FB3 CAN_F12R1_FB3_MskSYSCFG_EXTICR2_EXTI4_PE 0x00000004UtraceEVENT_GROUP_CLEAR_BITS(xEventGroup,uxBitsToClear) FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)CAN_F10R2_FB2_Pos (2U)CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)CAN_F6R2_FB23 CAN_F6R2_FB23_MskI2C_OAR1_ADD8 I2C_OAR1_ADD8_MskFSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)CAN_F0R2_FB28 CAN_F0R2_FB28_MskCAN_F5R1_FB15_Pos (15U)ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_MskLL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACENCAN_F6R2_FB6_Pos (6U)CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)CAN_TSR_TME1 CAN_TSR_TME1_MskUSB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)ETH_DMAIER_TUIE ETH_DMAIER_TUIE_MskDCMI_MIS_LINE_MIS_Pos (4U)TIM_EGR_UG_Pos (0U)CAN_FA1R_FACT26_Pos (26U)CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)ADC_CCR_TSVREFE ADC_CCR_TSVREFE_MskADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_MskETH_MACCR_BL ETH_MACCR_BL_MskUSB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)CAN_F13R2_FB1_Pos (1U)CAN_FS1R_FSC12 CAN_FS1R_FSC12_MskTIM_CCMR2_IC4F_Pos (12U)CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_MskETH_MACFCR_PLT_Minus28_Pos (4U)CAN_F6R1_FB12 CAN_F6R1_FB12_MskCAN_TSR_TXOK2_Pos (17U)CAN_TDL2R_DATA1_Pos (8U)FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk_GCC_STDINT_H ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)CAN_FFA1R_FFA20_Pos (20U)FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_MskCAN_F7R1_FB25_Pos (25U)CAN_F9R2_FB19 CAN_F9R2_FB19_MskCAN_TI0R_IDE CAN_TI0R_IDE_MskFSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)__FLT32_MAX_EXP__ 128SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)GPIO_MODER_MODER6_Pos (12U)CAN_F2R2_FB14 CAN_F2R2_FB14_MskLL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOPSYSCFG_EXTICR3_EXTI8_PF 0x00000005URCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_MskETH_MACCR_IFG_64Bit 0x00080000UADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_MskUSB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)FSMC_BTR1_CLKDIV_Pos (20U)IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8))ADC_CSR_STRT2_Pos (12U)TIM_SR_COMIF TIM_SR_COMIF_Msk__FLT32X_NORM_MAX__ 1.7976931348623157e+308F32xDMA1_Stream7_IRQnETH_DMAIER_TBUIE_Pos (2U)_GLIBCXX_HAVE_BUILTIN_IS_SAME 1FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_MskLL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2)GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2GPIO_ODR_OD3 0x00000008U__ARM_FP16_FORMAT_IEEEARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)SPI_SR_UDR SPI_SR_UDR_MskCAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)GPIO_MODER_MODER14_Pos (28U)CAN_F7R1_FB19_Pos (19U)CAN_TSR_TERR1_Pos (11U)USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)RCC_APB1LPENR_TIM5LPEN_Pos (3U)_UNBUF_STREAM_OPT 1EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)__UHA_IBIT__ 8_GLIBCXX_END_EXTERN_C }SPI_CR1_CRCEN SPI_CR1_CRCEN_MskRCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_MskLL_AHB1_GRP1_EnableClockLL_TIM_OSSI_DISABLE 0x00000000UADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)RTC_CR_ALRBE RTC_CR_ALRBE_MskRCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_MskETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_MskTIM_DIER_COMIE TIM_DIER_COMIE_MskDCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)ETH_MACCR_RD ETH_MACCR_RD_MskRCC_APB1RSTR_USART3RST_Pos (18U)vTaskGetTaskInfo vTaskGetInfoCAN_F6R2_FB11_Pos (11U)CAN_F11R1_FB15 CAN_F11R1_FB15_MskDAC_DHR12L2_DACC2DHR_Pos (4U)TPI_DEVID_PTINVALID_Pos 9UDCMI_ESUR_LEU DCMI_ESUR_LEU_MskEXTI_IMR_IM16 EXTI_IMR_MR16ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)CAN_F10R1_FB12_Pos (12U)SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_MskFSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)CRC_DR_DR_Pos (0U)LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)GPIO_IDR_ID15 0x00008000UETH_DMASR_NIS ETH_DMASR_NIS_MskGPIO_OSPEEDR_OSPEED7 0x0000C000UDMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)SDIO ((SDIO_TypeDef *) SDIO_BASE)CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)CAN_F9R1_FB29_Pos (29U)EXTI_PR_PR6_Pos (6U)ETH_DMAOMR_ST ETH_DMAOMR_ST_MskETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk_GLIBCXX_HAVE_LOG10F 1EXTI_RTSR_TR16 EXTI_RTSR_TR16_MskCAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)I2C_SR1_STOPF_Pos (4U)__cpp_lib_bitops 201907LpdFREERTOS_ERRNO_EISCONN 127CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8RTC_TSTR_MNU RTC_TSTR_MNU_MskDBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)LL_TIM_OSSR_DISABLE 0x00000000UUSB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)CAN_F11R2_FB22 CAN_F11R2_FB22_MskCAN_F4R1_FB15 CAN_F4R1_FB15_MskUSB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)USB_OTG_DEACHINT_IEP1INT_Pos (1U)CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)__need_NULLCAN_F2R1_FB9_Pos (9U)CAN_F12R1_FB22_Pos (22U)FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)CAN_F5R1_FB25 CAN_F5R1_FB25_MskCAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)SPI_CR2_TXEIE SPI_CR2_TXEIE_MskCAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)EXTI_PR_PR5_Pos (5U)CAN_F13R2_FB8 CAN_F13R2_FB8_MskLL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk_GLIBCXX_HAVE_AS_SYMVER_DIRECTIVE 1USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_MskDMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk__ptrvalue CAN_IER_SLKIE CAN_IER_SLKIE_MskGPIO_ODR_ODR_15 GPIO_ODR_OD15SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_MskIWDG_RLR_RL_Pos (0U)DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)TIM_CR2_MMS_Pos (4U)SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)CAN_F12R1_FB16_Pos (16U)DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)DMA_HIFCR_CFEIF7_Pos (22U)LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2ENFLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)EXTI_EMR_EM9 EXTI_EMR_MR9FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)LL_TIM_SLAVEMODE_DISABLED 0x00000000URTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)SYSCFG_EXTICR2_EXTI5_PH 0x00000070URTC_DR_YT_Pos (20U)EXTI_IMR_MR3 EXTI_IMR_MR3_MskLL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDSUSB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)ADC_CSR_STRT3 ADC_CSR_STRT3_MskEXTI_EMR_MR3_Pos (3U)ADC_DR_DATA_Pos (0U)SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)LL_DMA_ConfigAddressesCAN_F13R2_FB11 CAN_F13R2_FB11_MskFSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)xQueueSendFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )CAN_F7R1_FB11 CAN_F7R1_FB11_MskportENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )GPIO_OSPEEDR_OSPEED7_0 0x00004000UCAN_F1R1_FB16 CAN_F1R1_FB16_MskCAN_MSR_ERRI CAN_MSR_ERRI_MskRCC_APB1LPENR_PWRLPEN_Pos (28U)USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_MskETH_MACFCR_PLT_Minus144_Pos (5U)CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_MskDCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)CAN_F13R1_FB2_Pos (2U)FSMC_BTR1_DATLAT_Pos (24U)GPIO_OTYPER_OT10 0x00000400UETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_MskFSMC_BTR3_DATAST_Pos (8U)SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_MskUSB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_MskCAN_F2R1_FB15_Pos (15U)CAN_FM1R_FBM21_Pos (21U)CAN_F9R1_FB6_Pos (6U)ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)__lock_annotate(x) FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)USB_OTG_GINTSTS_CMOD_Pos (0U)CAN_F9R1_FB2 CAN_F9R1_FB2_MskFLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)USB_OTG_HCCHAR_EPDIR_Pos (15U)USB_OTG_GUSBCFG_SRPCAP_Pos (8U)USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)LL_MPU_REGION_NUMBER3 0x03UI2C1_ER_IRQnGPIO_PUPDR_PUPD15_0 0x40000000UADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)GPIO_BSRR_BR11 0x08000000ULL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)CAN_F6R2_FB30 CAN_F6R2_FB30_MskLL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2ENCAN_FM1R_FBM2_Pos (2U)RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_MskFLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_MskUSB_OTG_GINTSTS_ESUSP_Pos (10U)DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk_ZN4gpio3PinILm1073873920ELm5EEaSERKbLL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOPFSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_MskLL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)CAN_FM1R_FBM15_Pos (15U)FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_MskdecodeUSART_SR_PE USART_SR_PE_MskEXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)PWR_CSR_BRE PWR_CSR_BRE_MskCAN_F9R2_FB24_Pos (24U)CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_MskEXTI_FTSR_TR3 EXTI_FTSR_TR3_MskCAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)TIM_CR2_OIS3_Pos (12U)xQueueCreateStatic(uxQueueLength,uxItemSize,pucQueueStorage,pxQueueBuffer) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NEEXTI_SWIER_SWIER8_Pos (8U)USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)CAN_F13R2_FB12_Pos (12U)CAN_F7R2_FB4 CAN_F7R2_FB4_MskSDIO_ICR_DATAENDC_Pos (8U)CAN_F11R1_FB24_Pos (24U)DMA_HIFCR_CTEIF7_Pos (25U)TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_MskUSB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)cmainRCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_MskFSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)CAN_FFA1R_FFA17_Pos (17U)__CC_SUPPORTS___INLINE__ 1SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)CAN_RI1R_EXID CAN_RI1R_EXID_MskTPI_FFSR_FtNonStop_Pos 3U__USQ_IBIT__ 0_DEFAULT_SOURCE 1CAN_F4R1_FB19_Pos (19U)LL_GPIO_AF_3 (0x0000003U)RCC_APB1ENR_I2C2EN_Pos (22U)_STDDEF_H_ CAN_ESR_LEC_Pos (4U)_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))TIM_CR2_TI1S_Pos (7U)CAN_F1R1_FB31 CAN_F1R1_FB31_MskTPI_FIFO0_ITM_ATVALID_Pos 29UEXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0_GLIBCXX_PACKAGE_BUGREPORT ""RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)DAC_CR_EN1_Pos (0U)LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_MskSDIO_ARG_CMDARG_Pos (0U)ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)RCC_APB1LPENR_UART4LPEN_Pos (19U)CAN_FM1R_FBM9 CAN_FM1R_FBM9_MskADC_SMPR2_SMP5 ADC_SMPR2_SMP5_MskRTC_CR_ALRBE_Pos (9U)DMA2_Stream5_IRQnFSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)CAN_F11R2_FB17_Pos (17U)TIM_DIER_CC4DE_Pos (12U)CAN_F6R1_FB24 CAN_F6R1_FB24_MskRCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)traceBLOCKING_ON_QUEUE_SEND(pxQueue) SYSCFG_EXTICR1_EXTI1_PA 0x00000000UCAN_IER_ERRIE CAN_IER_ERRIE_MskRCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk_GLIBCXX_HAVE_STDINT_H 1I2C_DR_DR I2C_DR_DR_MskDMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)pdFREERTOS_ERRNO_EOPNOTSUPP 95CAN_F11R1_FB4 CAN_F11R1_FB4_MskUSB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)_ZN3srv12ProtocolImpl10dma_finishEb__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1USART_CR2_LBDL USART_CR2_LBDL_MskETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U__closureRCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)_GLIBCXX_HAVE_LIMIT_AS 0USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_MskI2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)ADC_HTR_HT ADC_HTR_HT_MskCAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)_USE_GDTOA TIM_CR1_UDIS TIM_CR1_UDIS_MskUSB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_MskGPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5WWDG_CR_T WWDG_CR_T_MskADC_CR1_AWDEN ADC_CR1_AWDEN_MskpdTASK_HOOK_CODE TaskHookFunction_tFSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)CAN_F4R2_FB7_Pos (7U)GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_MskSDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)ETH_DMABMR_RTPR_1_1 0x00000000UUSB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDISFSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)TIM_BDTR_AOE TIM_BDTR_AOE_Msk__INT_LEAST16_WIDTH__ 16_GLIBCXX23_CONSTEXPR ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)CAN_F2R1_FB15 CAN_F2R1_FB15_MskDMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_MskDT_RANGE_1 ((uint8_t)0x00)_GLIBCXX_BIT 1SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)CAN_TI1R_TXRQ_Pos (0U)CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)USB_OTG_GOTGCTL_ASVLD_Pos (18U)LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6ENETH_MACCR_IPCO_Pos (10U)USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_MskCAN_F5R2_FB15_Pos (15U)I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_MskCAN_F3R2_FB22_Pos (22U)CAN_F7R2_FB6_Pos (6U)__GCC_ATOMIC_BOOL_LOCK_FREE 2USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)CAN_MCR_AWUM_Pos (5U)RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)ETH_MACHTHR_HTH ETH_MACHTHR_HTH_MskSDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)INT_LEAST16_MAX __INT_LEAST16_MAX__RTC_DR_MU RTC_DR_MU_MskCAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)CAN_F3R1_FB6 CAN_F3R1_FB6_MskCAN_F10R2_FB6 CAN_F10R2_FB6_MsklistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) CAN_FS1R_FSC11_Pos (11U)DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)FSMC_BWTR4_DATAST_Pos (8U)FSMC_BTR3_ADDHLD_Pos (4U)TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)__NEWLIB_H__ 1WINT_MIN __WINT_MIN__CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3))EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)CAN_TDH0R_DATA6_Pos (16U)GPIO_MODER_MODE15_0 0x40000000UCAN_F8R1_FB10_Pos (10U)TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)RCC_CR_PLLON RCC_CR_PLLON_Msk__cpp_unicode_literals 200710LCAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)CAN_F13R1_FB7 CAN_F13R1_FB7_MskETH_MACPMTCSR_WFR_Pos (6U)USE_F2 1configENABLE_MPU 0IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))CAN_F11R1_FB26_Pos (26U)RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_MskCAN_F2R1_FB8 CAN_F2R1_FB8_MskADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)xSemaphoreCreateCountingStatic(uxMaxCount,uxInitialCount,pxSemaphoreBuffer) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk_GLIBCXX_HAVE_ACOSF 1USB_OTG_GINTMSK_OEPINT_Pos (19U)pdFREERTOS_ERRNO_ENXIO 6CAN_F1R2_FB8 CAN_F1R2_FB8_MsktraceTIMER_COMMAND_RECEIVED(pxTimer,xMessageID,xMessageValue) DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)ADC_SMPR2_SMP5_Pos (15U)CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)DMA_SxCR_DIR_Pos (6U)FLASH_OPTCR_nWRP_4 (0x010UL << FLASH_OPTCR_nWRP_Pos)CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))CAN_F3R2_FB20 CAN_F3R2_FB20_MskLL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1ENEXTI_PR_PR21 EXTI_PR_PR21_MskCAN_F9R2_FB17 CAN_F9R2_FB17_MskFSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)TypeSleepModeGPIO_ODR_ODR_6 GPIO_ODR_OD6USB_OTG_HCFG_FSLSS_Pos (2U)configUSE_APPLICATION_TASK_TAG 0RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)_GLIBCXX_USE_SC_NPROCESSORS_ONLN 1GPIO_BSRR_BS_10 GPIO_BSRR_BS10TIM_OR_TI4_RMP TIM_OR_TI4_RMP_MskUSB_OTG_HPRT_PSPD_Pos (17U)USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_MskGPIO_AFRH_AFSEL8_3 0x00000008U__cpp_lib_robust_nonmodifying_seq_ops 201304LCAN_TDH1R_DATA5 CAN_TDH1R_DATA5_MskDMA1_Stream2_BASE (DMA1_BASE + 0x040UL)FLASH_OPTCR_nWRP_2 (0x004UL << FLASH_OPTCR_nWRP_Pos)ETH_MACDBGR_TFF_Pos (25U)RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)CLEAR_REG(REG) ((REG) = (0x0))SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)EXTI_EMR_EM0 EXTI_EMR_MR0__UINT_FAST64_TYPE__ long long unsigned intFSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)CAN_F10R2_FB12_Pos (12U)RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)EXTI_IMR_IM22 EXTI_IMR_MR22ADC_CCR_VBATE ADC_CCR_VBATE_MskIS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)_GLIBCXX_NAMESPACE_LDBL_OR_CXX11 _GLIBCXX_NAMESPACE_CXX11CAN_FM1R_FBM19 CAN_FM1R_FBM19_MskRTC_CR_WUTE RTC_CR_WUTE_MskGPIO_MODER_MODE13 0x0C000000UucDummy5SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_MskUSB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)CFSRRCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)CAN_F12R2_FB9 CAN_F12R2_FB9_MskARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)CAN_F3R2_FB1 CAN_F3R2_FB1_MskFSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_MskUSB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)ETH_DMASR_ERS_Pos (14U)SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)CAN_F6R2_FB17 CAN_F6R2_FB17_MskRCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_MskLL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOPUSB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2CAN_F9R1_FB18 CAN_F9R1_FB18_MskTIM_CR1_CEN_Pos (0U)TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)DMA1 ((DMA_TypeDef *) DMA1_BASE)USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)__INTPTR_TYPE__ intDBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_MskADC_CSR_JSTRT2_Pos (11U)RTC_TAFCR_TAMPIE_Pos (2U)RTC_ALRMBR_ST RTC_ALRMBR_ST_MskRCC_BDCR_LSERDY_Pos (1U)__const constI2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)FLASH_SR_WRPERR FLASH_SR_WRPERR_MskDCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)_ZN5crash4draw10break_lineEPKctRCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_MskLL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)USB_OTG_HOST_CHANNEL_BASE 0x500ULEXTI_FTSR_TR15 EXTI_FTSR_TR15_MskUSB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)__cpp_sized_deallocation 201309LTPI_FFCR_TrigIn_Pos 8UUSB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_MskRTC_DR_DU_Pos (0U)ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)CAN_F12R2_FB21_Pos (21U)__detail_GLIBCXX_END_NAMESPACE_CXX11 }CAN_F6R1_FB31 CAN_F6R1_FB31_MskETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)__glibcxx_integral_traps falseFSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk_MACHINE__TYPES_H FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_MskCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)CAN_F12R2_FB16_Pos (16U)LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)CAN_F12R2_FB24 CAN_F12R2_FB24_MskRCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_MskCAN_F11R1_FB3_Pos (3U)SPI_CR1_RXONLY SPI_CR1_RXONLY_MskUSB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)CAN2_RX1_IRQnFSMC_PIO4_IOHOLD4_Pos (16U)CAN_BTR_SJW_Pos (24U)CAN_F7R1_FB7_Pos (7U)CAN_FS1R_FSC8_Pos (8U)USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_MskCAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_MsktraceTAKE_MUTEX_RECURSIVE_FAILED(pxMutex) FSMC_BCR4_WAITPOL_Pos (9U)pdFREERTOS_ERRNO_EINVAL 22__FLT64_MIN_10_EXP__ (-307)DMA_LIFCR_CFEIF2_Pos (16U)xPSR_V_Pos 28UCAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)__FLT_NORM_MAX__ 3.4028234663852886e+38FETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)RCC_APB1RSTR_I2C3RST_Pos (23U)GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)_GLIBCXX_USE_STD_SPEC_FUNCS 1__lock_close(lock) __retarget_lock_close(lock)TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)USB_OTG_HS_PERIPH_BASE 0x40040000ULETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)DAC_CR_WAVE1_Pos (6U)EXTI_PR_PR8 EXTI_PR_PR8_MskCAN_F0R1_FB1 CAN_F0R1_FB1_MskDMA_SxCR_PINCOS DMA_SxCR_PINCOS_MskTIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)PWR_CR_PLS_LEV0 0x00000000USCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_MskCAN_F2R1_FB22 CAN_F2R1_FB22_MskETH_MACDBGR_TFNE_Pos (24U)_GLIBCXX_USE_NOEXCEPT noexceptDMA_LISR_DMEIF2_Pos (18U)LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)PRERI2C_CR1_PE_Pos (0U)__IO volatileRTC_TSTR_ST RTC_TSTR_ST_MskRCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_MskLL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)CAN_F5R2_FB29 CAN_F5R2_FB29_MskADC_CR2_JSWSTART ADC_CR2_JSWSTART_MskUSB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)PWR_CR_CWUF_Pos (2U)FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)CAN_IER_TMEIE_Pos (0U)CAN_F3R1_FB18 CAN_F3R1_FB18_MskFSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_MskADC_SMPR2_SMP0_Pos (0U)__FLT32X_HAS_QUIET_NAN__ 1INCLUDE_xTaskAbortDelay 0ADC_CR2_DDS ADC_CR2_DDS_MskFSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_MskLL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)CAN_F5R1_FB10_Pos (10U)SCB_AIRCR_SYSRESETREQ_Pos 2UFSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)FSMC_PMEM2_MEMSET2_Pos (0U)DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)_ZN5crash14panic_nonfatalEPKcCAN_F11R2_FB14 CAN_F11R2_FB14_MskDCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_MskRNG_SR_SEIS_Pos (6U)CAN_FA1R_FACT21_Pos (21U)USART_CR3_SCEN_Pos (5U)ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)FSMC_BWTR2_ACCMOD_Pos (28U)ETH_MACCR_IPCO ETH_MACCR_IPCO_MskPWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_MskCAN_F3R1_FB0_Pos (0U)CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)ETH_MACPMTCSR_GU_Pos (9U)CAN_F7R2_FB15 CAN_F7R2_FB15_MskDBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)GPIO_BSRR_BS0 0x00000001USYSCFG_EXTICR1_EXTI0_PG 0x00000006UCAN_F6R2_FB31 CAN_F6R2_FB31_MskportNUM_CONFIGURABLE_REGIONS 1CAN_F10R1_FB5 CAN_F10R1_FB5_MskDAC_CR_BOFF2_Pos (17U)USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_MskmtCOVERAGE_TEST_DELAY() TIM_CR2_OIS3 TIM_CR2_OIS3_MskUSB_OTG_OUT_ENDPOINT_BASE 0xB00ULFSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)CAN_FA1R_FACT13 CAN_FA1R_FACT13_MskCAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)DAC_DHR12LD_DACC2DHR_Pos (20U)USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)USB_OTG_IN_ENDPOINT_BASE 0x900ULSYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_MskRCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)ETH_DMASR_TPSS ETH_DMASR_TPSS_MskETH_DMABMR_USP ETH_DMABMR_USP_MskxPSR_ISR_Msk (0x1FFUL )ETH_DMASR_EBS_Pos (23U)__CC_SUPPORTS_WARNING 1CAN_F0R1_FB27 CAN_F0R1_FB27_MskUSB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)EXTI_RTSR_TR6_Pos (6U)RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)RTC_CR_WUCKSEL RTC_CR_WUCKSEL_MskUSART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)SYSCFG_EXTICR1_EXTI2_PA 0x00000000UCAN_F2R2_FB8_Pos (8U)FLASH_ACR_LATENCY_0WS 0x00000000UCAN_FS1R_FSC15 CAN_FS1R_FSC15_MskCAN_RDL1R_DATA2 CAN_RDL1R_DATA2_MskCAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)RTC_DR_WDU RTC_DR_WDU_MskADC_CSR_JSTRT2 ADC_CSR_JSTRT2_MskETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_MskFSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)RCC_CFGR_PPRE2_DIV16 0x0000E000UCAN_TDH2R_DATA7_Pos (24U)USB_OTG_DIEPCTL_TXFNUM_Pos (22U)ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)CAN_F7R1_FB30 CAN_F7R1_FB30_MskconfigUSE_COUNTING_SEMAPHORES 1_GLIBCXX_HAVE_USLEEP 1FLASH_OPTCR_OPTSTRT_Pos (1U)GPIO_AFRL_AFSEL4_1 0x00020000URCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_MskMPU_TYPE_RALIASES 4UITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)GPIO_AFRH_AFSEL12_1 0x00020000UtraceQUEUE_PEEK_FROM_ISR(pxQueue) __ARM_FEATURE_COMPLEXSYSCFG_EXTICR2_EXTI4_PH 0x00000007U_T_PTRDIFF_ FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)EXTI_IMR_IM2 EXTI_IMR_MR2_ecbssCAN_F5R2_FB7_Pos (7U)I2C_OAR1_ADD1 I2C_OAR1_ADD1_MskLL_DMA_MDATAALIGN_BYTE 0x00000000USDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2ENRTC_ALRMAR_HU_Pos (16U)TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)_GLIBCXX_BEGIN_NAMESPACE_LDBL_OR_CXX11 _GLIBCXX_BEGIN_NAMESPACE_CXX11I2C_OAR1_ADD3_Pos (3U)CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)CAN_F12R1_FB25 CAN_F12R1_FB25_MskRCC_APB1LPENR_SPI3LPEN_Pos (15U)CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)_REENT_INC(_ptr) ((_ptr)->_inc)GPIO_BSRR_BR_2 GPIO_BSRR_BR2portBYTE_ALIGNMENT_MASK ( 0x0007 )ETH_MACCR_CSD_Pos (16U)RNG_SR_DRDY_Pos (0U)I2C_CR1_SWRST I2C_CR1_SWRST_MskDMA_HISR_TCIF5_Pos (11U)FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)PUPDRUSART_GTPR_PSC_Pos (0U)ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)CAN_F3R1_FB21 CAN_F3R1_FB21_MskCAN_F12R1_FB8 CAN_F12R1_FB8_Msk_GLIBCXX_HAVE_COSHF 1CoreDebug_DEMCR_TRCENA_Pos 24UUSART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UEXTI_IMR_MR21 EXTI_IMR_MR21_Msk_GLIBCXX20_DEPRECATED [[__deprecated__]]USART_CR1_TCIE_Pos (6U)DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)__FLT_HAS_INFINITY__ 1I2C_OAR1_ADDMODE_Pos (15U)ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_MskLL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_MskUSB_OTG_GINTSTS_DATAFSUSP_Pos (22U)RTC_BKP3R_Pos (0U)GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0USART_CR3_DMAT USART_CR3_DMAT_MskADC_CR1_DISCEN ADC_CR1_DISCEN_MskCAN_F9R1_FB18_Pos (18U)FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)SYSCFG_EXTICR3_EXTI8_PI 0x00000008UFSMC_BCR1_WAITPOL_Pos (9U)UINT_FAST16_MAX __UINT_FAST16_MAX__GPIO_PUPDR_PUPD3_1 0x00000080ULL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_MskADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)DCMI_ICR_VSYNC_ISC_Pos (3U)DMA_HIFCR_CTCIF7_Pos (27U)CAN_F11R1_FB20 CAN_F11R1_FB20_MskportSOFTWARE_BARRIER() CAN_F8R2_FB10_Pos (10U)CAN_IER_BOFIE CAN_IER_BOFIE_MskLL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)__SFRACT_MAX__ 0X7FP-7HRDCMI_RISR_ERR_RIS DCMI_RIS_ERR_RISCAN_FM1R_FBM23_Pos (23U)RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)CAN_F12R1_FB11_Pos (11U)GPIO_AFRH_AFSEL10_1 0x00000200UETH_DMASR_AIS_Pos (15U)LL_TIM_TS_ITR0 0x00000000UCAN_TDT1R_DLC_Pos (0U)traceSTREAM_BUFFER_SEND_FAILED(xStreamBuffer) DAC_BASE (APB1PERIPH_BASE + 0x7400UL)FSMC_PCR2_PWAITEN_Pos (1U)FLASH_OPTCR_OPTLOCK_Pos (0U)TIM_CR1_CKD_Pos (8U)portENTER_CRITICAL() vPortEnterCritical()LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSENEXTI_EMR_MR12 EXTI_EMR_MR12_MskDCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)CAN_F1R2_FB0_Pos (0U)RCC_AHB3LPENR_FSMCLPEN_Pos (0U)ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)ETH_DMABMR_FB ETH_DMABMR_FB_MskDCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)I2C_SR2_TRA_Pos (2U)ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_MskxSTATIC_MINI_LIST_ITEMtraceTIMER_CREATE(pxNewTimer) _GLIBCXX_USE_INIT_PRIORITY_ATTRIBUTE 1EXTI_IMR_MR20_Pos (20U)RTC_ALRMBR_MSK3_Pos (23U)DMA_SxCR_MSIZE_Pos (13U)DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)CAN_FS1R_FSC2 CAN_FS1R_FSC2_MskGPIO_BSRR_BS_11 GPIO_BSRR_BS11GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_MskFSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)CAN_TSR_TERR1 CAN_TSR_TERR1_MskLL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM__cpp_rvalue_references 200610LETH_PTPTSSR_TSSO_Pos (4U)USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)ETH_MACA2HR_MBC_Pos (24U)ETH_DMAOMR_RTC_128Bytes 0x00000018U__glibcxx_requires_sorted_set(_First1,_Last1,_First2) EXTI_IMR_MR14_Pos (14U)DCMI_RIS_FRAME_RIS_Pos (0U)EXTI_RTSR_TR9 EXTI_RTSR_TR9_MskCAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)DBGMCU_BASE 0xE0042000ULDMA2_Stream5_BASE (DMA2_BASE + 0x088UL)ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)PeriphsCAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)LL_DMA_STREAM_0 0x00000000UETH_MACA1HR_MBC_Pos (24U)_ZN5crash5cmainEPKcmmmGPIO_MODER_MODE14 0x30000000UDMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)portDOUBLE doubleCAN_FM1R_FBM10_Pos (10U)FSMC_BCR1_MWID_Pos (4U)CAN_TI0R_STID_Pos (21U)_REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed)EXTI_RTSR_TR22_Pos (22U)xMemoryRegion MemoryRegion_t__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))GPIO_MODER_MODE1_0 0x00000004UCAN_F10R1_FB10 CAN_F10R1_FB10_MskCAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)RTC_ISR_TSF_Pos (11U)RTC_TR_HU_Pos (16U)RCC_CIR_LSERDYF_Pos (1U)RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)GPIO_MODER_MODER4 GPIO_MODER_MODER4_MskCAN_F7R2_FB22 CAN_F7R2_FB22_MskADC_CR1_OVRIE_Pos (26U)CAN_MCR_NART CAN_MCR_NART_MskCAN_TI2R_STID CAN_TI2R_STID_MskUSB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_MskUsageFault_IRQnCAN_RDH1R_DATA6_Pos (16U)RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)EXTI_RTSR_TR15 EXTI_RTSR_TR15_MskCAN_TSR_ALST2_Pos (18U)CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)I2C_CR2_ITBUFEN_Pos (10U)CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)_GLIBCXX_FWDREF(_Tp) _Tp&&CAN_F1R2_FB16_Pos (16U)CAN_F5R1_FB8_Pos (8U)EXTI_RTSR_TR16_Pos (16U)NVIC_EnableIRQ __NVIC_EnableIRQIS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM10) || ((INSTANCE) == TIM11) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM13) || ((INSTANCE) == TIM14))SDIO_STA_CTIMEOUT_Pos (2U)DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)ETH_DMABMR_USP_Pos (23U)CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)FSMC_BWTR1_ACCMOD_Pos (28U)USB_OTG_GINTMSK_DISCINT_Pos (29U)USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)CAN_F2R1_FB21_Pos (21U)GPIO_OSPEEDR_OSPEED11_0 0x00400000UUSART_BRR_DIV_Mantissa_Pos (4U)INT_FAST32_MINSDIO_STA_CMDACT SDIO_STA_CMDACT_MskconfigPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)ETH_DMATDLAR_STL ETH_DMATDLAR_STL_MskRCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)DWT_CTRL_FOLDEVTENA_Pos 21UCAN_TI0R_IDE_Pos (2U)__INT_MAX__ 0x7fffffff__ARM_FEATURE_DSPTIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)I2C_SR1_TIMEOUT_Pos (14U)TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)GPIO_OSPEEDR_OSPEED4_0 0x00000100UARM_MPU_CACHEP_WB_NWA 3ULL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUTFLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)CAN_F3R2_FB13 CAN_F3R2_FB13_MskTIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)GPIO_PUPDR_PUPD10_0 0x00100000U__INTPTR_MAX__ 0x7fffffffCAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)ETH_DMASR_TPS_Waiting_Pos (21U)RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)FLASH_OPTCR_WDG_SW_Pos (5U)CAN_F4R1_FB31_Pos (31U)SCB_DFSR_DWTTRAP_Pos 2UUSB_OTG_HOST_BASE 0x400ULSIZE_MAX __SIZE_MAX__TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_MskCAN1_SCE_IRQnCAN_F7R1_FB16 CAN_F7R1_FB16_MskLL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUTRTC_TSTR_SU_Pos (0U)ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)SCB_VTOR_TBLBASE_Pos 29URCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_MskLL_GPIO_AF_5 (0x0000005U)__ULLFRACT_EPSILON__ 0x1P-64ULLRCAN_F8R2_FB18 CAN_F8R2_FB18_MskGPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)CAN_FFA1R_FFA23_Pos (23U)GPIO_OSPEEDR_OSPEED14_1 0x20000000UTIM_DMAR_DMAB TIM_DMAR_DMAB_MskEXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_MskFLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)SCB_AIRCR_VECTKEYSTAT_Pos 16UFLASH_ACR_DCRST FLASH_ACR_DCRST_MskDMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)CAN_F4R1_FB25_Pos (25U)FSMC_SR4_ILS_Pos (1U)CAN_F10R2_FB27 CAN_F10R2_FB27_MskLL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1)__cpp_generic_lambdas 201707L__builtin_memcpySYSCFG_EXTICR2_EXTI5_PF 0x00000050UFSMC_BWTR4_DATAST_3 (0x08UL << FSMC_BWTR4_DATAST_Pos)CAN_F1R1_FB1_Pos (1U)__RESTRICT __restrictUSART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)CAN1_RX1_IRQnLL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOPCAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)SYSCFG_EXTICR1_EXTI3_PG 0x00006000URCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)_GLIBCXX_PACKAGE_STRING "package-unused version-unused"ADC_CR2_ADON ADC_CR2_ADON_MskADC_SQR1_L ADC_SQR1_L_MskDBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)_GLIBCXX_HAVE_SYS_TIME_H 1_REENT_IS_NULL(_ptr) ((_ptr) == NULL)ADC_SMPR1_SMP15_Pos (15U)_ZN5crash4draw4textERNS_6MatrixEPKctthUSB_OTG_HCDMA_DMAADDR_Pos (0U)USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_MskLL_TIM_BREAK_DISABLE 0x00000000UDAC_DOR1_DACC1DOR_Pos (0U)LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1PCAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)CAN_F7R1_FB6 CAN_F7R1_FB6_MskETH_MACMIIAR_CR_Div42 0x00000000UUSART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk__bounded CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)CAN_F0R2_FB9_Pos (9U)CAN_F3R2_FB11_Pos (11U)ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_MskSPI_CR1_LSBFIRST_Pos (7U)ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)FSMC_BCR2_WREN_Pos (12U)USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)ADC_CSR_DOVR1 ADC_CSR_OVR1GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)SYSCFG_EXTICR2_EXTI7_PI 0x00008000U__glibcxx_requires_partitioned_upper_pred(_First,_Last,_Value,_Pred) USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk__ARM_FPCAN_F8R2_FB21 CAN_F8R2_FB21_MskpdMS_TO_TICKS(xTimeInMs) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )CAN_F12R2_FB16 CAN_F12R2_FB16_MskCAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)CAN_F2R2_FB26 CAN_F2R2_FB26_MskCAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)CAN_F8R2_FB7 CAN_F8R2_FB7_MskFSMC_BWTR4_DATAST_0 (0x01UL << FSMC_BWTR4_DATAST_Pos)SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)TIM_CCMR2_OC4M TIM_CCMR2_OC4M_MskSDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_MskEXTI_SWIER_SWIER18_Pos (18U)TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)USART_CR3_SCEN USART_CR3_SCEN_MskCAN_F3R2_FB8_Pos (8U)CAN_F5R2_FB8 CAN_F5R2_FB8_MskTPI_DEVID_MinBufSz_Pos 6U_NOINLINE __attribute__ ((__noinline__))TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)DMA2_Stream0_IRQnUSB_OTG_DOEPMSK_EPDM_Pos (1U)SYSCFG_EXTICR2_EXTI7_PF 0x00005000UFSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)TIM_CCMR1_OC1M TIM_CCMR1_OC1M_MskUSB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_MskRCC_AHB1LPENR_GPIOFLPEN_Pos (5U)CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)CAN_F11R1_FB15_Pos (15U)USB_OTG_HPRT_POCCHNG_Pos (5U)SYSCFG_EXTICR1_EXTI3_PA 0x00000000UFSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_MskCAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)CAN_F8R1_FB10 CAN_F8R1_FB10_MskCAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3)CAN_F11R1_FB9 CAN_F11R1_FB9_MskSCB_DFSR_EXTERNAL_Pos 4UDCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)RTC_ALRMAR_MNU_Pos (8U)CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)xPSR_Q_Msk (1UL << xPSR_Q_Pos)ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)CAN_F4R2_FB12 CAN_F4R2_FB12_MskEXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk__APCS_32__ 1DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)SYSCFG_EXTICR2_EXTI7_PC 0x00002000UGPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2INCLUDE_xTaskGetSchedulerState 1RTC_TR_PM RTC_TR_PM_MskportFORCE_INLINE inline __attribute__( ( always_inline ) )DWT_CTRL_CYCCNTENA_Msk (0x1UL )USART_CR3_IRLP_Pos (2U)RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_MskCAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)TIM_DIER_CC2DE_Pos (10U)USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_MskETH_DMABMR_PBL ETH_DMABMR_PBL_MskGPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)CAN_F7R2_FB31_Pos (31U)RTC_ISR_ALRAWF_Pos (0U)CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RISTIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)CAN_F7R2_FB1 CAN_F7R2_FB1_MskCAN_F1R2_FB17 CAN_F1R2_FB17_MskETH_DMABMR_FPM ETH_DMABMR_FPM_MskDAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)FSMC_BCR2_WREN FSMC_BCR2_WREN_MskLL_GPIO_PIN_14 GPIO_BSRR_BS_14__ARM_ARCH_GLIBCXX11_USE_C99_MATH 1FSMC_PATT4_ATTWAIT4_Pos (8U)FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_MskqueueSEND_TO_FRONT ( ( BaseType_t ) 1 )CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)ADC_CSR_AWD1_Pos (0U)DWT_CTRL_NUMCOMP_Pos 28UITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)start_outGPIO_AFRL_AFSEL5 0x00F00000UADC_SQR3_SQ5 ADC_SQR3_SQ5_MskCAN_F9R2_FB18_Pos (18U)LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)EXTI_EMR_MR0 EXTI_EMR_MR0_MskCAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)I2C_OAR2_ADD2_Pos (1U)CAN_F13R1_FB19_Pos (19U)ADC_SR_AWD_Pos (0U)SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_MskGPIO_BSRR_BS6 0x00000040USPI_CR1_BR SPI_CR1_BR_MskCAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)__SSP_FORTIFY_LEVEL 0CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)PWR_CSR_PVDO PWR_CSR_PVDO_MskCAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)ETH_DMACHTBAR_HTBAP_Pos (0U)CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)TIM_CCMR1_OC1PE_Pos (3U)EXTI_EMR_MR12_Pos (12U)ITM_LSR_Present_Msk (1UL )CAN_FM1R_FBM24 CAN_FM1R_FBM24_MskUINT_LEAST16_MAXconfigASSERT(x) do { if (!(x)) msign_panic("assert failed"); } while(0)__arm__ 1CAN_F10R1_FB28 CAN_F10R1_FB28_MskPRIVILEGED_DATA GPIO_BSRR_BS12 0x00001000UGPIO_IDR_ID13 0x00002000UTIM_SR_CC3IF_Pos (3U)__glibcxx_requires_partitioned_lower(_First,_Last,_Value) EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)TIM_CNT_CNT TIM_CNT_CNT_MskCAN_F1R1_FB18 CAN_F1R1_FB18_MskRTC_TR_ST_Pos (4U)EXTI_PR_PR17_Pos (17U)portGET_HIGHEST_PRIORITY(uxTopPriority,uxReadyPriorities) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)ADC_SQR1_SQ15 ADC_SQR1_SQ15_MskRCC_APB1RSTR_SPI2RST_Pos (14U)MODELSERVE_GLOBAL__sub_I__ZN5crash6matrixEGPIO_IDR_ID14 0x00004000URCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)CAN_F1R1_FB25_Pos (25U)DCMI_CWSIZE_VLINE_Pos (16U)__cpp_lambdas 200907LFSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)CAN_F1R1_FB28 CAN_F1R1_FB28_MskFLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)DMA_HISR_HTIF6 DMA_HISR_HTIF6_MskRTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)USB_OTG_GINTMSK_ESUSPM_Pos (10U)RTC_ISR_WUTWF_Pos (2U)USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)USB_OTG_DOEPCTL_CNAK_Pos (26U)FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_MskSCB_SHCSR_MEMFAULTACT_Pos 0USPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)ETH_DMASR_TUS ETH_DMASR_TUS_MskCAN_F4R1_FB1 CAN_F4R1_FB1_MskCAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)__attribute_malloc__ CAN_FS1R_FSC5 CAN_FS1R_FSC5_MskLL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_MskEXTI_FTSR_TR20 EXTI_FTSR_TR20_Mskmblt1ADC_CR1_JAUTO_Pos (10U)ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)CAN_F1R1_FB8 CAN_F1R1_FB8_MskCAN_RI0R_STID_Pos (21U)RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_MskRTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)CAN_TI0R_TXRQ_Pos (0U)TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)USART_CR1_RE_Pos (2U)CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)FLASH_ACR_BYTE2_ADDRESS_Pos (0U)DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)CAN_MSR_SAMP_Pos (10U)CAN_F0R2_FB11_Pos (11U)__restrict_arr TIM_SMCR_ETPS_Pos (12U)CAN_F12R2_FB22_Pos (22U)LL_SYSCFG_EXTI_PORTB (uint32_t)1RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_MskDMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)FLASH_ACR_LATENCY_Pos (0U)RTC_TR_MNU_Pos (8U)EXC_RETURN_HANDLER (0xFFFFFFF1UL)PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)CAN_F3R1_FB3 CAN_F3R1_FB3_MskUSB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_MskSPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)CAN_F6R1_FB29_Pos (29U)ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2CAN_F2R2_FB3 CAN_F2R2_FB3_MskCAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk_GLIBCXX_HAVE_LIMIT_FSIZE 0RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)CAN_FA1R_FACT9 CAN_FA1R_FACT9_MskTIM_SR_CC3IF TIM_SR_CC3IF_MskTIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)AHB3LPENRCAN_F3R1_FB29_Pos (29U)RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)CAN_ESR_REC_Pos (24U)TIM8_TRG_COM_TIM14_IRQnDMA_LISR_TEIF3_Pos (25U)panic_from_isrGPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)ETH_MACA3HR_AE ETH_MACA3HR_AE_MskCAN_F2R1_FB16 CAN_F2R1_FB16_MskRCC_CR_PLLRDY RCC_CR_PLLRDY_MskDCMI_RIS_VSYNC_RIS_Pos (3U)USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)EXTI_IMR_MR1 EXTI_IMR_MR1_Msk_GLIBCXX11_DEPRECATED _GLIBCXX_DEPRECATEDCAN_F2R2_FB21_Pos (21U)PWR_CR_CSBF_Pos (3U)STREAM_OFFSET_TABETH_MACFFR_PM ETH_MACFFR_PM_MskCAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)__INT_FAST8_WIDTH__ 32ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)CAN_F2R1_FB5 CAN_F2R1_FB5_MskCAN_FA1R_FACT10_Pos (10U)FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_MskFSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)CAN_F1R2_FB5 CAN_F1R2_FB5_MskUSB_OTG_DOEPMSK_B2BSTUP_Pos (6U)DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_MskCAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)SIG_ATOMIC_MIN __SIG_ATOMIC_MIN__USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)__DBL_DIG__ 15USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_MskI2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)RTC_CR_ADD1H_Pos (16U)SRAM_BASE SRAM1_BASEFuncSCB_AIRCR_VECTCLRACTIVE_Pos 1UUSB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk_END_STD_C }GPIO_IDR_IDR_7 GPIO_IDR_ID7WWDG_IRQnSCB_SHCSR_MEMFAULTENA_Pos 16UUSB_OTG_DOEPCTL_EPENA_Pos (31U)RNG_CR_IE RNG_CR_IE_MskCAN_FA1R_FACT21 CAN_FA1R_FACT21_MskDCMI_DR_BYTE2_Pos (16U)CAN_F2R2_FB15_Pos (15U)IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)_GLIBCXX_USE_WCHAR_T 1USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL )CAN_F8R2_FB5 CAN_F8R2_FB5_MskDMA_SxCR_CHSEL DMA_SxCR_CHSEL_MskUSB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk__INT_WIDTH__ 32DCMI_IER_OVR_IE_Pos (1U)USART_CR3_DMAT_Pos (7U)TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)EXTI_IMR_MR2_Pos (2U)FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)DMA_SxFCR_FEIE DMA_SxFCR_FEIE_MskFSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)PWR_CR_PLS_LEV5 0x000000A0UCAN_TSR_ALST2 CAN_TSR_ALST2_MskTIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)_GLIBCXX_USE_C99_STDLIB _GLIBCXX11_USE_C99_STDLIBSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_ICSR_ISRPREEMPT_Pos 23USDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_MskFSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)CAN_RI1R_STID CAN_RI1R_STID_MskCAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)EXTI_EMR_MR18_Pos (18U)RCC_AHB1RSTR_GPIOGRST_Pos (6U)EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)INC_FREERTOS_H CAN_RDT1R_DLC CAN_RDT1R_DLC_MskCAN_F11R2_FB11_Pos (11U)UINT64_MAX __UINT64_MAX__CAN_F8R1_FB22 CAN_F8R1_FB22_MskADC_SQR2_SQ8_Pos (5U)ETH_DMASR_TS ETH_DMASR_TS_MskRCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_MskUSB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)CAN_MCR_TTCM CAN_MCR_TTCM_MskADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)RCC_AHB1LPENR_CRCLPEN_Pos (12U)ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0HardFault_IRQnUSB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_MskRTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)__compiler_membar() __asm __volatile(" " : : : "memory")_GLIBCXX_UTILITY_H 1CAN_F7R2_FB25_Pos (25U)ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)GPIO_BSRR_BS13 0x00002000URCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)UART4_IRQnpdFALSE ( ( BaseType_t ) 0 )USART3_IRQnFSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)ETH_DMABMR_RTPR_3_1 0x00008000ULL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_MskLL_TIM_OSSI_ENABLE TIM_BDTR_OSSIRCC_APB1RSTR_CAN2RST_Pos (26U)FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)TIM_CCER_CC2P TIM_CCER_CC2P_MskRTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)CAN_F4R2_FB19_Pos (19U)CAN_RDH0R_DATA7_Pos (24U)__ULACCUM_EPSILON__ 0x1P-32ULKRTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)CAN_F9R1_FB13_Pos (13U)RTC_ALRMBR_PM RTC_ALRMBR_PM_MskCAN_F7R1_FB20_Pos (20U)traceSTREAM_BUFFER_CREATE_FAILED(xIsMessageBuffer) CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk_ZN5crash20MatrixBitLookupTableILj0EEC4EvUSB_OTG_DIEPMSK_TXFURM_Pos (8U)FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_MskDMA_SxCR_TEIE DMA_SxCR_TEIE_MskLL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)EXTI_PR_PR11 EXTI_PR_PR11_Msk_POSIX_SOURCE 1CAN_F1R2_FB9_Pos (9U)USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)__LDBL_MIN_EXP__ (-1021)RCC_CIR_LSERDYF RCC_CIR_LSERDYF_MskSPI_CR1_MSTR_Pos (2U)RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)ETH_DMABMR_FPM_Pos (24U)SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_MskxTaskNotifyStateClearIndexed(xTask,uxIndexToClear) xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)EXTI_FTSR_TR16_Pos (16U)SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)ETH_DMAIER_AISE_Pos (15U)SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_MskGPIO_OTYPER_OT9 0x00000200UGPIO_BSRR_BR8 0x01000000UCAN_F12R1_FB30 CAN_F12R1_FB30_MskDMA_LISR_FEIF3_Pos (22U)SYSCFG_EXTICR1_EXTI2_PC 0x00000200UCAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)GPIO_PUPDR_PUPD8_1 0x00020000U__SHRT_WIDTH__ 16USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)FLASH_ACR_LATENCY_2WS 0x00000002UCAN_F6R2_FB29_Pos (29U)FSMC_PCR2_ECCEN_Pos (6U)ETH_MACCR_BL_4 0x00000040UDAC_CR_TSEL2_Pos (19U)configPOST_SLEEP_PROCESSING(x) CAN_F10R1_FB9 CAN_F10R1_FB9_MskCAN_F9R1_FB30_Pos (30U)DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)ETH_MACCR_DM_Pos (11U)EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)__FLT32_MIN__ 1.1754943508222875e-38F32CAN_RF1R_FMP1_Pos (0U)GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)MPU ((MPU_Type *) MPU_BASE )__ARM_BF16_FORMAT_ALTERNATIVE__USACCUM_FBIT__ 8CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)__OBSOLETE_MATH __OBSOLETE_MATH_DEFAULT_ELIDABLE_INLINE static __inline__CAN_F0R1_FB24 CAN_F0R1_FB24_MskFSMC_PCR2_PTYP_Pos (3U)SPI_CR1_CPOL SPI_CR1_CPOL_MskUSB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_MskETH_DMASR_TPS ETH_DMASR_TPS_Msk__lock_acquire(lock) __retarget_lock_acquire(lock)DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)ETH_DMAIER_FBEIE_Pos (13U)USB_OTG_DTHRCTL_RXTHREN_Pos (16U)CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)__LDBL_EPSILON__ 2.2204460492503131e-16LRTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)CAN_F12R2_FB2_Pos (2U)RTC_CR_POL RTC_CR_POL_MskDCMI_CR_EDM_0 0x00000400UPARCELSCAN_F0R1_FB29_Pos (29U)TIM_SR_BIF TIM_SR_BIF_MskCAN_F8R2_FB6_Pos (6U)USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_MskCAN_TSR_ABRQ0 CAN_TSR_ABRQ0_MskI2C1 ((I2C_TypeDef *) I2C1_BASE)SPI_CR2_ERRIE_Pos (5U)EXTI_SWIER_SWIER0_Pos (0U)I2C_CR1_SMBTYPE_Pos (3U)__cpp_template_auto 201606LRCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)CAN_F6R2_FB28 CAN_F6R2_FB28_MskSDIO_STA_SDIOIT SDIO_STA_SDIOIT_MskSCB_CFSR_BUSFAULTSR_Pos 8UxTaskNotifyStateClear(xTask) xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_MskCAN_F13R1_FB20 CAN_F13R1_FB20_MskDMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)CoreDebug_DCRSR_REGWnR_Pos 16USDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)ADC_CR2_JEXTSEL_Pos (16U)GPIO_BSRR_BR_6 GPIO_BSRR_BR6SDIO_CMD_WAITINT SDIO_CMD_WAITINT_MskARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)__INT_LEAST32_TYPE__ long intxQueueSetMemberHandle QueueSetMemberHandle_tDMA_SxCR_PSIZE DMA_SxCR_PSIZE_MskLL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2EXTI_FTSR_TR2_Pos (2U)CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)__FLT_HAS_DENORM__ 1ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)USB_OTG_TX0FD USB_OTG_TX0FD_MskFSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)CAN_F7R1_FB2_Pos (2U)CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)_GLIBCXX98_USE_C99_WCHAR 1DWT ((DWT_Type *) DWT_BASE )DMA_HISR_TEIF5 DMA_HISR_TEIF5_MskUSB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_MskLL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)configUSE_MUTEXES 1EXTI_RTSR_TR11_Pos (11U)RCC_APB1LPENR_I2C2LPEN_Pos (22U)USB_OTG_DCFG_DAD_Pos (4U)listTEST_LIST_INTEGRITY(pxList) GPIO_IDR_ID6 0x00000040UCAN_F11R2_FB26_Pos (26U)SYSCFG_EXTICR4_EXTI12_PB 0x00000001URCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_MskRCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)LL_TIM_SR_CC3IF TIM_SR_CC3IF_GLIBCXX_ATOMIC_BUILTINS 1I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)FLASH_CR_MER_Pos (2U)CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)CAN_F2R2_FB19 CAN_F2R2_FB19_MskDAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)_EXCEPTION_DEFINES_H 1ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)GPIO_MODER_MODE3_0 0x00000040UFLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)_GLIBCXX_HAVE_SINF 1GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3CAN_F6R1_FB6 CAN_F6R1_FB6_MskETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || ((INSTANCE) == USB_OTG_HS))USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)CoreDebug_DHCSR_C_STEP_Pos 2UCAN_F2R1_FB10_Pos (10U)GPIO_MODER_MODE15_1 0x80000000UCAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)_GLIBCXX17_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk__opsEXTI_PR_PR20_Pos (20U)USB_OTG_GOTGINT_SRSSCHG_Pos (8U)FSMC_PCR3_PWID_Pos (4U)LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBMETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)SCB_CCR_DIV_0_TRP_Pos 4U_GLIBCXX_MOVE_BACKWARD3(_Tp,_Up,_Vp) std::move_backward(_Tp, _Up, _Vp)FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)LISR__RCSID(s) struct __hackEXTI_IMR_IM9 EXTI_IMR_MR9RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)GPIO_MODER_MODE5 0x00000C00UDMA_LIFCR_CTEIF3_Pos (25U)CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)EXTI_RTSR_TR20 EXTI_RTSR_TR20_MskRCC_APB2ENR_TIM1EN_Pos (0U)TIM_CCR3_CCR3 TIM_CCR3_CCR3_MskUSART_CR1_TE_Pos (3U)DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)CAN_F8R2_FB11_Pos (11U)__SIZEOF_DOUBLE__ 8RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)FSMC_BTR4_ADDSET_Pos (0U)RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)traceBLOCKING_ON_STREAM_BUFFER_RECEIVE(xStreamBuffer) USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_MskCAN_F3R2_FB18 CAN_F3R2_FB18_MskCAN_F1R2_FB19_Pos (19U)EXTI_PR_PR14_Pos (14U)GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3__ACCUM_FBIT__ 15TIM_DIER_COMDE_Pos (13U)RTC_TSTR_HU RTC_TSTR_HU_MskGPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3GPIO_OSPEEDR_OSPEED11_1 0x00800000UGPIO_PUPDR_PUPD1_0 0x00000004UCAN_F4R1_FB20_Pos (20U)USB_OTG_DOEPCTL_EPDIS_Pos (30U)FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk__DEFINED_size_t RCC_APB2RSTR_SPI1RST_Pos (12U)_REENT_CVTBUF(_ptr) ((_ptr)->_cvtbuf)ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_MskLL_DMA_DisableFifoModeDMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_MskGPIO_LCKR_LCK6_Pos (6U)FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)I2C_SR1_ADD10_Pos (3U)CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_MskCAN_FFA1R_FFA12_Pos (12U)SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST__UINT_FAST16_TYPE__ unsigned intRTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)__INT_LEAST8_WIDTH__ 8RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)CAN_F4R1_FB14_Pos (14U)ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_MskportTICK_TYPE_EXIT_CRITICAL() USB_OTG_GRXSTSP_EPNUM_Pos (0U)CAN_F4R1_FB20 CAN_F4R1_FB20_MskCAN_F3R2_FB29_Pos (29U)SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)CAN_F2R2_FB17 CAN_F2R2_FB17_MskINCLUDE_xQueueGetMutexHolder 0MPU_RASR_SIZE_Pos 1UCAN_F6R1_FB30_Pos (30U)DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)CAN_TDT2R_DLC CAN_TDT2R_DLC_MskCAN_F7R2_FB27 CAN_F7R2_FB27_MskCAN_F12R1_FB3_Pos (3U)CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)pcQueueGetName(xQueue) _GLIBCXX98_USE_C99_MATH 1RCC_APB1LPENR_CAN2LPEN_Pos (26U)ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)USART_SR_PE_Pos (0U)TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)__ISO_C_VISIBLE 2020CAN_F8R1_FB7_Pos (7U)configCHECK_FOR_STACK_OVERFLOW 1CAN_F3R2_FB0_Pos (0U)ETH_DMAOMR_OSF ETH_DMAOMR_OSF_MskSDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_MskCAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)LL_GPIO_ReadReg(__INSTANCE__,__REG__) READ_REG(__INSTANCE__->__REG__)_Noreturn [[noreturn]]PLLCFGRTIM_CCMR1_CC2S_Pos (8U)MatrixBitLookupTableGPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk_GLIBCXX_HAVE_ATANF 1GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_MskCAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)LL_TIM_EnableIT_UPDATEEXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)__OPTIMIZE__ 1GPIO_BSRR_BR7 0x00800000UCAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)ARM_MPU_CACHEP_NOCACHE 0UIS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)CAN_F6R1_FB24_Pos (24U)RCC_AHB1ENR_ETHMACRXEN_Pos (27U)USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_MskUINT8_C(c) __UINT8_C(c)_GLIBCXX_DEFAULT_ABI_TAG _GLIBCXX_ABI_TAG_CXX11LL_TIM_EnableDMAReq_UPDATECAN_F13R2_FB26 CAN_F13R2_FB26_MskRCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_MskCAN_RDH1R_DATA7 CAN_RDH1R_DATA7_MskDMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_MskFSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)TIM_BDTR_LOCK TIM_BDTR_LOCK_MskCAN_F0R1_FB11 CAN_F0R1_FB11_MskCAN_F9R2_FB8 CAN_F9R2_FB8_MskI2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)USB_OTG_GINTSTS_NPTXFE_Pos (5U)USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_MskETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)CAN_F9R2_FB13 CAN_F9R2_FB13_MskTIM_CCMR2_IC3F TIM_CCMR2_IC3F_MskTPI_FFSR_FtStopped_Pos 1UDAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)__cpp_range_based_for 201603LCAN_F5R1_FB12 CAN_F5R1_FB12_MskCAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)DCMI_CWSTRT_HOFFCNT_Pos (0U)basePriEXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)FSMC_BCR1_WAITCFG_Pos (11U)SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)__INT_FAST32_MAX__ 0x7fffffffGPIO_BSRR_BR6 0x00400000UCAN_FM1R_FBM3_Pos (3U)CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)CAN_FFA1R_FFA5_Pos (5U)RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_MskIS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)PortEXTI_FTSR_TR12 EXTI_FTSR_TR12_MskDMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk__FLT32X_HAS_DENORM__ 1CAN_F5R2_FB10_Pos (10U)CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WSFSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk_RAND48_MULT_2 (0x0005)_INITIALIZER_LIST CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_MskSCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_MskUSB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_MskEXTI_IMR_IM18 EXTI_IMR_MR18CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)SCB_ICSR_NMIPENDSET_Pos 31U_GLIBCXX_HAVE_SYS_RESOURCE_H 1EXTI_FTSR_TR8 EXTI_FTSR_TR8_MskCAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)CAN_F4R1_FB0_Pos (0U)GPIO_OSPEEDR_OSPEED1_1 0x00000008UCAN_F8R1_FB28_Pos (28U)RCC_APB1ENR_WWDGEN_Pos (11U)RTC_DR_DT RTC_DR_DT_MskRCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_MskTIM8_UP_TIM13_IRQn_PSTL_EARLYEXIT_PRESENT (__INTEL_COMPILER >= 1800)CAN_F2R2_FB7 CAN_F2R2_FB7_Msk__DBL_MAX_EXP__ 1024CAN_FA1R_FACT15 CAN_FA1R_FACT15_MskCAN_F2R1_FB25_Pos (25U)ADC_CR2_EXTEN_Pos (28U)xTaskNotifyAndQueryFromISR(xTaskToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )ETH_MMCRIMR_RFCEM_Pos (5U)CAN_RDL0R_DATA1_Pos (8U)FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)CAN_F7R2_FB20_Pos (20U)I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk__unreachable() __builtin_unreachable()FLASH_OPTCR_nWRP_7 (0x080UL << FLASH_OPTCR_nWRP_Pos)CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)__cpp_impl_three_way_comparison 201907LI2C_SR1_STOPF I2C_SR1_STOPF_MskEXTI_IMR_MR0 EXTI_IMR_MR0_MskETH_MACDBGR_TFWA_Pos (22U)LL_DMA_EnableStreamFSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)SPI_CR1_MSTR SPI_CR1_MSTR_MskGPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)CAN_FS1R_FSC0_Pos (0U)USART_CR3_CTSIE USART_CR3_CTSIE_MskTIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)TIM_DIER_COMDE TIM_DIER_COMDE_MskSysTick_CTRL_CLKSOURCE_Pos 2U_Alignof(x) alignof(x)__cpp_variadic_using 201611LUSB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_MskDMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_MskSYSCFG_EXTICR2_EXTI5_PD 0x00000030URTC_BKP4R RTC_BKP4R_MskSDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_MskCAN_F7R2_FB14_Pos (14U)CAN_F6R1_FB29 CAN_F6R1_FB29_MskCAN_F11R2_FB4 CAN_F11R2_FB4_MskDAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)traceQUEUE_SEND(pxQueue) CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)RCC_CR_PLLI2SON RCC_CR_PLLI2SON_MskFSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)CAN_F10R2_FB3_Pos (3U)ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_MskCAN_F13R1_FB31_Pos (31U)MPU_RBAR_ADDR_Pos 5UCAN_F6R2_FB7_Pos (7U)__ARM_FEATURE_CRC32LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIENCAN_F11R2_FB11 CAN_F11R2_FB11_MskF_CPU 120000000LTIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk_GCC_PTRDIFF_T TIM_BDTR_MOE_Pos (15U)__INT_FAST16_WIDTH__ 32ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_MskETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)RTC_BKP15R_Pos (0U)__CMSIS_GCC_H CAN_F13R2_FB2_Pos (2U)CAN_F8R1_FB1 CAN_F8R1_FB1_MskCAN_F1R1_FB14_Pos (14U)uxItemsCAN_F13R1_FB25_Pos (25U)RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKDAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)CAN_F9R2_FB6_Pos (6U)USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_MskRCC_APB1ENR_TIM12EN_Pos (6U)__INT_FAST16_MAX__ 0x7fffffff__SCHAR_MAX__ 0x7fRCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)__INT_FAST64_MAX__ 0x7fffffffffffffffLLI2C_CR1_STOP_Pos (9U)LL_GPIO_AF_4 (0x0000004U)_REENT_GETLOCALENAME_L_BUF(ptr) ((ptr)->_new._reent._getlocalename_l_buf)CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)__RCSID_SOURCE(s) struct __hackCAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_MskRCC_CR_HSEON RCC_CR_HSEON_MskLL_SYSCFG_EXTI_PORTE (uint32_t)4ETH_DMAOMR_TTC_16Bytes 0x0001C000UUSB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)__CM3_REV 0x0200URCC_CFGR_HPRE_DIV512 0x000000F0USYSCFG_EXTICR2_EXTI5_PB 0x00000010UGPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0PendRequestTypeget_task_regs_GLIBCXX_PACKAGE_NAME "package-unused"RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)CAN_F12R2_FB31 CAN_F12R2_FB31_MskRTC_DR_YU_Pos (16U)SPI_SR_UDR_Pos (3U)CAN_F7R1_FB3 CAN_F7R1_FB3_MskI2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)LL_TIM_InitFSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)CAN_F6R2_FB3 CAN_F6R2_FB3_MskCAN_F3R1_FB24_Pos (24U)GPIO_MODER_MODER1_Pos (2U)CAN_F1R1_FB31_Pos (31U)ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_MskDMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_MskFSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)CAN_F12R2_FB11_Pos (11U)EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)SPI_CR1_SSM SPI_CR1_SSM_MskRCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_MskCAN_F1R2_FB7_Pos (7U)__INT64_C(c) c ## LLRCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)ETH_DMAIER_NISE_Pos (16U)USART_CR3_DMAR USART_CR3_DMAR_Msk__UNALIGNED_UINT16_WRITE(addr,val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)RCC_PLLCFGR_PLLSRC_Pos (22U)CAN_F2R2_FB0_Pos (0U)RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)PWR_CR_CSBF PWR_CR_CSBF_MskLL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_MskTIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)CAN_F3R1_FB18_Pos (18U)RCC_CFGR_SW RCC_CFGR_SW_MskGPIO_MODER_MODE0_1 0x00000002UGPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9CAN_RF0R_FULL0_Pos (3U)CAN_F5R2_FB5 CAN_F5R2_FB5_MskCAN_F12R1_FB22 CAN_F12R1_FB22_MskFSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)_REENT_INIT(var) { 0, &__sf[0], &__sf[1], &__sf[2], 0, "", _REENT_INIT_RESERVED_1 _NULL, _REENT_INIT_RESERVED_0 _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { _REENT_INIT_RESERVED_2 _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_RESERVED_6_7 _NULL }USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)__CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)USART_CR2_STOP_Pos (12U)CAN_F9R2_FB20 CAN_F9R2_FB20_MskGPIO_BSRR_BS_12 GPIO_BSRR_BS12CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)LL_MAX_DELAY 0xFFFFFFFFUSYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_MskSCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)FSMC_BTR1_ACCMOD_Pos (28U)__DEFINED_wchar_t GPIO_OSPEEDR_OSPEED8_1 0x00020000UCAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_MskCAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)ETH_MMCTIMR_TGFM_Pos (21U)FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)USART_CR2_ADD_Pos (0U)update_or_read_calibrationETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)_MB_CAPABLE 1ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk__glibcxx_requires_irreflexive(_First,_Last) traceTASK_SWITCHED_OUT() ITM_BASE (0xE0000000UL)RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_MskCAN_F7R1_FB28 CAN_F7R1_FB28_MskETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U__cpp_alias_templates 200704LCAN_F5R1_FB28_Pos (28U)__FRACT_IBIT__ 0USB_OTG_GAHBCFG_GINT_Pos (0U)I2C_SR2_PEC I2C_SR2_PEC_MskETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_MskCAN_F13R1_FB2 CAN_F13R1_FB2_MskLL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)USB_OTG_DIEPCTL_SNAK_Pos (27U)FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)SysTick_BASE (SCS_BASE + 0x0010UL)FSMC_BTR4_DATAST_Pos (8U)CAN_F12R2_FB31_Pos (31U)RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)CAN_F5R2_FB11 CAN_F5R2_FB11_MskDMA_LISR_TCIF0 DMA_LISR_TCIF0_MsktskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )SDIO_CLKCR_PWRSAV_Pos (9U)PROTOCOL_H CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)__DBL_MIN_10_EXP__ (-307)pxContainer pvContainer_STL_ITERATOR_BASE_TYPES_H 1TIM_CR1_OPM TIM_CR1_OPM_MskDBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_MskCAN_F10R1_FB4_Pos (4U)USART_CR2_LINEN USART_CR2_LINEN_MskAutoreload__ARM_FEATURE_CLZ 1DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)SIG_ATOMIC_MAXLL_DMA_STREAM_ALL 0xFFFF0000UFSMC_PCR4_PTYP FSMC_PCR4_PTYP_MskGPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11RTC_CALIBR_DCS_Pos (7U)__glibcxx_floating(_Tp,_Fval,_Dval,_LDval) (std::__are_same<_Tp, float>::__value ? _Fval : std::__are_same<_Tp, double>::__value ? _Dval : _LDval)CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)RTC_CR_SUB1H RTC_CR_SUB1H_MskEXTI_RTSR_TR15_Pos (15U)GPIO_BSRR_BR4 0x00100000UESP_USART_Port GPIOGGPIO_LCKR_LCK14 GPIO_LCKR_LCK14_MskFSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15CAN_F3R1_FB19 CAN_F3R1_FB19_MskETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)pdFREERTOS_ERRNO_ENOSPC 28LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXENGPIO_LCKR_LCK13_Pos (13U)LL_TIM_EnableCounterGPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_MskUSB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)RCC_CFGR_SWS_HSE 0x00000004UDBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_MskFSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)RCC_CFGR_RTCPRE_Pos (16U)ETH_MACFFR_SAF ETH_MACFFR_SAF_MskCAN_F13R1_FB3_Pos (3U)__ARM_FEATURE_LDREX 7CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)RTC_BKP8R_Pos (0U)__UINT8_TYPE__ unsigned char_PSTL_PRAGMA_MESSAGE_POLICIES(x) RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)DAC_CR_DMAEN1 DAC_CR_DMAEN1_MskRCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_MskCAN_F9R1_FB7_Pos (7U)ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_MskI2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)_REENT_SIG_FUNC(_ptr) ((_ptr)->_sig_func)CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)DMA_LISR_TCIF3_Pos (27U)CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)RCC_BDCR_LSEON RCC_BDCR_LSEON_MskRCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)traceQUEUE_SET_SEND traceQUEUE_SENDDBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)_GLIBCXX_END_NAMESPACE_VERSION ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)_GLIBCXX_HAVE_INTTYPES_H 1_BSD_WCHAR_T_ CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)traceEVENT_GROUP_CLEAR_BITS_FROM_ISR(xEventGroup,uxBitsToClear) USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)CAN_F6R2_FB24_Pos (24U)GPIO_PUPDR_PUPD12_0 0x01000000UCAN_F1R1_FB7 CAN_F1R1_FB7_MskCAN_F4R2_FB31_Pos (31U)DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_MskRCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_MskSDIO_DCTRL_RWSTOP_Pos (9U)FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_MskETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)CAN_F0R2_FB7 CAN_F0R2_FB7_MskADC_CSR_JEOC1 ADC_CSR_JEOC1_MskCAN_F10R1_FB25_Pos (25U)ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)ADC_SMPR1_SMP12_Pos (6U)USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)CAN_F12R2_FB6 CAN_F12R2_FB6_MskCAN_F3R2_FB3_Pos (3U)_GLIBCXX20_CONSTEXPR constexprUSART_SR_LBD USART_SR_LBD_MskRTC_TSDR_WDU_Pos (13U)CAN_F13R1_FB1 CAN_F13R1_FB1_MskUSB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_MskTPI_TRIGGER_TRIGGER_Pos 0UTIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_MskDMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)_GLIBCXX_HAVE_HYPOT 1USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)EXTI_SWIER_SWIER9_Pos (9U)LL_DMA_FIFOSTATUS_0_25 0x00000000URTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)TIM_RCR_REP TIM_RCR_REP_MskCAN_F6R2_FB18_Pos (18U)DCMI_IER_OVR_IE DCMI_IER_OVR_IE_MskFSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk__FLT32_IS_IEC_60559__ 1SPI_CR2_TXDMAEN_Pos (1U)GPIO_ODR_ODR_7 GPIO_ODR_OD7CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)CAN_F10R1_FB19_Pos (19U)CAN_F0R1_FB9 CAN_F0R1_FB9_MskCAN_IER_FFIE0 CAN_IER_FFIE0_MskCAN_F2R1_FB1_Pos (1U)DCMI_RIS_ERR_RIS_Pos (2U)__ATOMIC_ACQ_REL 4USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_MskCAN_F4R2_FB24 CAN_F4R2_FB24_MskDCMI_SR_HSYNC_Pos (0U)USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_MskDMA_LIFCR_CTCIF3_Pos (27U)_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)CAN_F13R2_FB29 CAN_F13R2_FB29_Msk__GNUC_EXECUTION_CHARSET_NAME "UTF-8"EXTI_IMR_IM4 EXTI_IMR_MR4RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)EXTI_EMR_EM1 EXTI_EMR_MR1DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)_PSTL_PRAGMA_SIMD_ORDERED_MONOTONIC_2ARGS(PRM1,PRM2) GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)configSTACK_DEPTH_TYPE uint16_tFSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)SCB_AIRCR_ENDIANESS_Pos 15UUSB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_MskETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)traceTIMER_COMMAND_SEND(xTimer,xMessageID,xMessageValueValue,xReturn) USB_OTG_FS_TOTAL_FIFO_SIZE 1280UADC_CSR_OVR2_Pos (13U)CAN_F4R2_FB18 CAN_F4R2_FB18_MskETH_DMAIER_RBUIE_Pos (7U)CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)CAN_F5R1_FB0_Pos (0U)APSR_N_Msk (1UL << APSR_N_Pos)CAN_F8R2_FB28_Pos (28U)SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)CAN_F13R2_FB28 CAN_F13R2_FB28_MskUSB_OTG_GUSBCFG_TRDT_Pos (10U)DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_MskFSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)CAN_F12R1_FB29_Pos (29U)__WINT_TYPE__ unsigned intRCC_CIR_HSIRDYIE_Pos (10U)FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_MskDCMI_CR_FCRC_1 0x00000200UGPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)USB_OTG_GINTMSK_OTGINT_Pos (2U)MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)ETH_DMAOMR_RTC_32Bytes 0x00000008UETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)TIM_CCMR2_OC3CE_Pos (7U)CAN_F10R2_FB0 CAN_F10R2_FB0_MskCAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)RSERVED1ETH_MMCRGUFCR_RGUFC_Pos (0U)__REGISTER_PREFIX__ USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_MskCAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)CAN_F11R2_FB21_Pos (21U)LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_MskITM_IRR_ATREADYM_Msk (1UL )RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1ETH_MMCCR_CR_Pos (0U)CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOPCAN_RDL1R_DATA0 CAN_RDL1R_DATA0_MskCAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_MskLL_TIM_DIER_CC3IE TIM_DIER_CC3IEFSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_MskCAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)USART_CR3_RTSE USART_CR3_RTSE_MskUSB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_MskGPIO_BSRR_BS2 0x00000004UCAN_F3R2_FB24_Pos (24U)FSMC_BTR4_ADDHLD_Pos (4U)TIM_EGR_BG TIM_EGR_BG_Msk__INT_LEAST64_WIDTH__ 64_T_WCHAR CAN_F4R1_FB19 CAN_F4R1_FB19_MskCAN_F11R2_FB15_Pos (15U)_GLIBCXX23_DEPRECATED_SUGGEST(ALT) PWR_CR_PDDS_Pos (1U)CAN_RDT0R_DLC_Pos (0U)CAN_F13R2_FB18 CAN_F13R2_FB18_MskUSB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)CAN_F11R2_FB3_Pos (3U)DWT_CTRL_POSTPRESET_Pos 1UCAN_F13R2_FB31_Pos (31U)APB1PERIPH_BASE PERIPH_BASEGPIO_MODER_MODER0 GPIO_MODER_MODER0_MskCAN_F7R2_FB7_Pos (7U)FLASH_OPTCR_nWRP_8 (0x100UL << FLASH_OPTCR_nWRP_Pos)CAN_F0R1_FB30 CAN_F0R1_FB30_MskCAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)configUSE_STATS_FORMATTING_FUNCTIONS 0CAN_TDT0R_TGT CAN_TDT0R_TGT_MskCAN_F9R1_FB14_Pos (14U)USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_MskUSB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)EXTI9_5_IRQnLL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMSETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk_STL_HEAP_H 1ETH_DMABMR_EDE_Pos (7U)RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)CAN_F10R2_FB19 CAN_F10R2_FB19_MskUSB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)I2C_SR2_DUALF I2C_SR2_DUALF_MskCAN_F13R2_FB25_Pos (25U)CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_MskIS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || ((INSTANCE) == SPI3))FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)CAN_F13R2_FB24 CAN_F13R2_FB24_MskGPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13MPU_RASR_S_Pos 18UUSB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)FLASH_SR_PGPERR FLASH_SR_PGPERR_MskCAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_MskGPIO_MODER_MODE12_0 0x01000000USDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)CAN_TI2R_TXRQ CAN_TI2R_TXRQ_MskRTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_MskFSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)CAN_F9R1_FB21 CAN_F9R1_FB21_MskDMAR_ZN5crash6Matrix14timer_finishedEvCAN_F3R1_FB26 CAN_F3R1_FB26_MskEXTI_PR_PR6 EXTI_PR_PR6_Msk_GLIBCXX_NODISCARD [[__nodiscard__]]USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)CAN_FS1R_FSC27 CAN_FS1R_FSC27_MskSYSCFG_EXTICR4_EXTI12_PE 0x00000004UDMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)FSMC_BWTR4_DATAST_6 (0x40UL << FSMC_BWTR4_DATAST_Pos)ADC_CCR_DELAY ADC_CCR_DELAY_MskUSB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)SRAM2_BASE 0x2001C000ULRCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)LL_DMA_PBURST_SINGLE 0x00000000UFSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_MskGPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)__glibcxx_class_requires(_a,_b) USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_MskFSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)DMAxSIG_ATOMIC_MINETH_DMABMR_PBL_4xPBL_8Beat 0x01000200UCAN_F8R1_FB20 CAN_F8R1_FB20_MskCAN_F1R2_FB31_Pos (31U)INCLUDE_uxTaskGetStackHighWaterMark2 0USART_BRR_DIV_Fraction_Pos (0U)make_opSPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)USART_CR1_WAKE_Pos (11U)TIM_CCER_CC2E TIM_CCER_CC2E_MskxPSR_N_Msk (1UL << xPSR_N_Pos)DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)__STRING(x) #xUSB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_MskFSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)GPIO_PUPDR_PUPD3_0 0x00000040UGPIO_OSPEEDR_OSPEED12_0 0x01000000UFSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)ADC_CSR_AWD2_Pos (8U)__ULLFRACT_MIN__ 0.0ULLRDCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIENGPIO_OSPEEDR_OSPEED2_0 0x00000010UARM_MPU_AP_NONE 0UDBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)SPI_CR1_BR_Pos (3U)GPIO_AFRL_AFSEL0_1 0x00000002UETH_MACA2HR_MBC_HBits7_0 0x10000000UCAN_F1R2_FB25_Pos (25U)RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk__ARM_ARCH_7M__ 1GPIO_MODER_MODER10_Pos (20U)EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXENDWT_FUNCTION_LNK1ENA_Pos 9UEXTI_FTSR_TR22_Pos (22U)CAN_F8R2_FB19 CAN_F8R2_FB19_MskNONEFSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_MskDCMI_DR_BYTE0 DCMI_DR_BYTE0_MskGPIO_BSRR_BS_13 GPIO_BSRR_BS13__DSBLL_TIM_TS_ITR1 TIM_SMCR_TS_0LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2ENRTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)_RAND48_SEED_1 (0xabcd)SPI_I2SCFGR_PCMSYNC_Pos (7U)FLASH_ACR_LATENCY_6WS 0x00000006USPI_I2SPR_ODD_Pos (8U)FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)xSTATIC_LISTLL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)CAN_F4R2_FB31 CAN_F4R2_FB31_MskGPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1CAN_F6R1_FB13_Pos (13U)GPIO_AFRH_AFSEL14 0x0F000000USCB_CCR_NONBASETHRDENA_Msk (1UL )DMA_HISR_FEIF6 DMA_HISR_FEIF6_MskETH_DMABMR_PBL_Pos (8U)I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)USB_OTG_DCTL_GONSTS_Pos (3U)CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)DMA1_Stream5_IRQnChannelTIM9 ((TIM_TypeDef *) TIM9_BASE)CAN_F4R1_FB9_Pos (9U)RCC_CFGR_HPRE_DIV4 0x00000090UDCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)DCMI_ICR_LINE_ISC_Pos (4U)EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)TIM_CR2_TI1S TIM_CR2_TI1S_Msk__FLT_RADIX__ 2SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_MskFSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)portUSING_MPU_WRAPPERS 0CAN_F11R1_FB8_Pos (8U)I2C_SR2_TRA I2C_SR2_TRA_Msk__INT16_TYPE__ short intEXTI_IMR_IM3 EXTI_IMR_MR3CAN_FS1R_FSC24_Pos (24U)USB_OTG_HCSPLT_PRTADDR_Pos (0U)traceCREATE_COUNTING_SEMAPHORE() CAN_FM1R_FBM21 CAN_FM1R_FBM21_MskETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_MskCAN_F10R1_FB25 CAN_F10R1_FB25_MskRCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)SYSCFG_EXTICR3_EXTI14_PH 0x00000700UCAN_F11R1_FB4_Pos (4U)__INT_LEAST8_TYPE__ signed charFSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_MskCAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)CAN_F13R1_FB19 CAN_F13R1_FB19_MskFSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)CAN_F8R1_FB23_Pos (23U)CAN_F7R1_FB8_Pos (8U)CAN_FS1R_FSC9_Pos (9U)_GLIBCXX_HAVE_EXPF 1FSMC_PATT2_ATTWAIT2_Pos (8U)CAN_F13R2_FB31 CAN_F13R2_FB31_MskFSMC_BTR4_DATLAT_Pos (24U)I2C_OAR1_ADD2 I2C_OAR1_ADD2_MskRTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)CAN_F0R2_FB22 CAN_F0R2_FB22_MskSPI_I2SCFGR_I2SSTD_Pos (4U)SYSCFG_EXTICR3_EXTI15_PH 0x00007000USCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)CAN_F4R1_FB11_Pos (11U)SCB_CFSR_USGFAULTSR_Pos 16U__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))RTC_WUTR_WUT_Pos (0U)_GLIBCXX_BEGIN_NAMESPACE_VERSION TIM8_CC_IRQnRCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)CAN_TSR_TXOK0 CAN_TSR_TXOK0_MskADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)ADC_JSQR_JSQ2_Pos (5U)USB_OTG_DOEPINT_B2BSTUP_Pos (6U)FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)strobe__cpp_lib_type_identity 201806LRCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)CAN_F8R1_FB17_Pos (17U)GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2CAN_F4R1_FB25 CAN_F4R1_FB25_MskRCC_CFGR_SW_HSE 0x00000001UEXTI_SWIER_SWIER13_Pos (13U)CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_MskDBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_MskCAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)RCC ((RCC_TypeDef *) RCC_BASE)RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)__FRACT_FBIT__ 15DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_MskCAN_FS1R_FSC CAN_FS1R_FSC_MskTPI_FIFO0_ETM_ATVALID_Pos 26U_GLIBCXX_TXN_SAFE __CONCAT1(x,y) x ## yFSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_MskFSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_MskFSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)USART_SR_TC USART_SR_TC_MskLL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1GPIO_AFRL_AFSEL3_3 0x00008000UCAN_F12R1_FB14 CAN_F12R1_FB14_MskDMA_SxCR_PBURST DMA_SxCR_PBURST_MskLL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3ENADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)CAN_F11R1_FB10_Pos (10U)__cpp_lib_destroying_delete 201806LETH_MACDBGR_TFRS_WRITING_Pos (20U)TPI_FIFO0_ITM_bytecount_Pos 27UDMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep( xExpectedIdleTime )MPU_RASR_SRD_Pos 8UFSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)RCC_APB1RSTR_TIM5RST_Pos (3U)GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2_ATEXIT_DYNAMIC_ALLOC 1__PACKED __attribute__((packed, aligned(1)))USB_OTG_DCFG_PERSCHIVL_Pos (24U)LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0FLASH_SR_EOP_Pos (0U)RTC_CR_WUTIE_Pos (14U)ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)snprintfFSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)__LOCK_INIT_RECURSIVE(class,lock) __LOCK_INIT(class,lock)FSMC_BCR2_BURSTEN_Pos (8U)RCC_CIR_HSERDYF_Pos (3U)USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk__inline inlineCAN_F0R1_FB16 CAN_F0R1_FB16_MskFSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)RCC_CFGR_SWS RCC_CFGR_SWS_MskCAN_RDH1R_DATA5 CAN_RDH1R_DATA5_MskCAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)EXTI_EMR_EM13 EXTI_EMR_MR13CAN_F10R2_FB19_Pos (19U)RCC_CR_PLLI2SON_Pos (26U)NDTRCAN_F12R2_FB21 CAN_F12R2_FB21_MskLL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)CAN_F3R1_FB1_Pos (1U)ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)SYSCFG_EXTICR3_EXTI9_PI 0x00000080UCAN_F13R1_FB20_Pos (20U)RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)GPIOC ((GPIO_TypeDef *) GPIOC_BASE)LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12ENTIM_CR1_ARPE_Pos (7U)USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk__glibcxx_requires_can_increment(_First,_Size) USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_MskDBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)__FLT32X_MIN__ 2.2250738585072014e-308F32x_NOINLINE_STATIC _NOINLINE staticCoreDebug_DEMCR_MON_EN_Pos 16ULL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2CAN_F1R2_FB1_Pos (1U)__WCHAR_MAX__ 0xffffffffULL_SYSCFG_EXTI_PORTH (uint32_t)7pdFREERTOS_ERRNO_ENMFILE 89CAN_F5R2_FB30 CAN_F5R2_FB30_MskADC_SMPR2_SMP4_Pos (12U)SDIO_RESP2_CARDSTATUS2_Pos (0U)_GLIBCXX_USE_CONSTEXPR constexprCAN_F9R2_FB13_Pos (13U)EXTI_EMR_EM17 EXTI_EMR_MR17CAN_FMR_FINIT CAN_FMR_FINIT_MskADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)__PTRDIFF_TYPE__ intRTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)ADC_CSR_STRT1_Pos (4U)CAN_F13R1_FB14_Pos (14U)EXTI_RTSR_TR7_Pos (7U)UART_DMA DMA2USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_MskRNG_SR_CECS_Pos (1U)EXTI_RTSR_TR3 EXTI_RTSR_TR3_MskCAN_F12R2_FB29_Pos (29U)CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)listCURRENT_LIST_LENGTH(pxList) ( ( pxList )->uxNumberOfItems )LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGENFSMC_BCR4_WREN_Pos (12U)CAN_F8R1_FB18_Pos (18U)RCC_APB1RSTR_TIM3RST_Pos (1U)DMA_LIFCR_CTCIF0_Pos (5U)CAN_F8R2_FB24_Pos (24U)CoreDebug_BASE (0xE000EDF0UL)ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_MskCAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk__has_feature(x) 0CAN_MSR_RX CAN_MSR_RX_MskETH_MMCCR_CR ETH_MMCCR_CR_MskCAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)_GLIBCXX_USE_C99_CTYPE_TR1 1SPI_CR1_SPE_Pos (6U)GPIO_OTYPER_OT8 0x00000100USDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_MskFSMC_PCR3_ECCEN_Pos (6U)CAN_F13R2_FB2 CAN_F13R2_FB2_MskADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)ADC_SQR1_L_Pos (20U)CAN_F5R2_FB8_Pos (8U)USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_MskUSB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)GPIO_OSPEEDR_OSPEED7_1 0x00008000URTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)CAN_F1R2_FB21 CAN_F1R2_FB21_MskCAN_F1R1_FB20_Pos (20U)GPIO_IDR_ID2 0x00000004UCAN_RI0R_RTR_Pos (1U)CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)I2C_OAR1_ADD4_Pos (4U)CAN_IER_LECIE CAN_IER_LECIE_MskRNG_SR_CECS RNG_SR_CECS_MskFSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingCAN_F9R2_FB5 CAN_F9R2_FB5_MskRTC_ALRMBR_HU RTC_ALRMBR_HU_MskADC_JOFR4_JOFFSET4_Pos (0U)__LDBL_NORM_MAX__ 1.7976931348623157e+308LUSB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_MskSPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_MskTIM_BDTR_DTG TIM_BDTR_DTG_Msk__UHA_FBIT__ 8GPIO_AFRH_AFSEL9_2 0x00000040UETH_PTPTSLUR_TSUPNS_Pos (31U)RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_MskFSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)RCC_PLLCFGR_PLLQ_Pos (24U)DAC_DHR12L1_DACC1DHR_Pos (4U)configUSE_CO_ROUTINES 0CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)CAN_F1R1_FB10 CAN_F1R1_FB10_MskTIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)_BSD_SIZE_T_ TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)MPU_TYPE_SEPARATE_Msk (1UL )__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1CAN_F3R1_FB30_Pos (30U)DMA_HIFCR_CTCIF5_Pos (11U)CAN_F4R2_FB17 CAN_F4R2_FB17_MskCAN_F9R1_FB1_Pos (1U)INT64_MINFSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_MskCAN_TDL2R_DATA3 CAN_TDL2R_DATA3_MskCAN_F6R2_FB19 CAN_F6R2_FB19_Msk__UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)xQueueReset(xQueue) xQueueGenericReset( xQueue, pdFALSE )ETH_DMABMR_DSL_Pos (2U)FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)USART_GTPR_GT_Pos (8U)ITM_IWR_ATVALIDM_Pos 0UEXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_MskUSB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_MskLL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000ETH_PTPTSSR_TSTTR_Pos (5U)CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)_PSTL_CPP14_2RANGE_MISMATCH_EQUAL_PRESENT (_MSC_VER >= 1900 || __cplusplus >= 201300L || __cpp_lib_robust_nonmodifying_seq_ops == 201304)_NEW RCC_APB2LPENR_ADC2LPEN_Pos (9U)CRC_IDR_IDR CRC_IDR_IDR_MskGPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1CAN_F5R1_FB17_Pos (17U)ETH_MACA3HR_MBC_Pos (24U)_MACHINE__DEFAULT_TYPES_H CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)DMA_SxFCR_FTH_Pos (0U)RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)UINT_FAST8_MAXSCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WSUSB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_MskUSB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_MskETH_MACCR_IFG_72Bit 0x00060000USPI_I2SCFGR_DATLEN_Pos (1U)CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)pdFREERTOS_ERRNO_EIO 5ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk_RAND48_MULT_1 (0xdeec)USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)ETH_MACDBGR_MSFRWCS_Pos (1U)USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_MskCAN_TI1R_STID_Pos (21U)CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)SubPriorityconfigMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)CAN_F6R1_FB5 CAN_F6R1_FB5_MskEXTI_PR_PR2 EXTI_PR_PR2_MskTIM_SR_CC1IF TIM_SR_CC1IF_MskEXTI_EMR_MR8 EXTI_EMR_MR8_MskLL_TIM_BREAK_ENABLE TIM_BDTR_BKECAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_MskADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)9NVIC_TypeCAN_F7R1_FB27_Pos (27U)CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_MskETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_MskCAN_F2R2_FB10_Pos (10U)_STL_PAIR_H 1GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)CAN_TDH1R_DATA7_Pos (24U)TIM13 ((TIM_TypeDef *) TIM13_BASE)LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1PETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)ETH_MACFFR_RA ETH_MACFFR_RA_MskUSB_OTG_DOEPCTL_SNAK_Pos (27U)FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)CAN_F5R1_FB7 CAN_F5R1_FB7_MskUSART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)TIM_SMCR_ETP TIM_SMCR_ETP_MskDCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)RCC_AHB3ENR_FSMCEN_Pos (0U)CAN_F4R2_FB7 CAN_F4R2_FB7_MskRCC_APB1RSTR_DACRST_Pos (29U)CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)__glibcxx_max_digits10(_Tp) (2 + __glibcxx_floating(_Tp, __FLT_MANT_DIG__, __DBL_MANT_DIG__, __LDBL_MANT_DIG__) * 643L / 2136)GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)EXTI_EMR_MR13_Pos (13U)IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM5))USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)CAN_F9R2_FB25 CAN_F9R2_FB25_Msk_GLIBCXX_HAVE_WCHAR_H 1__requires_exclusive(...) __lock_annotate(exclusive_locks_required(__VA_ARGS__))CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_MskTIM_EGR_CC4G_Pos (4U)CAN_F4R2_FB20_Pos (20U)tracePEND_FUNC_CALL(xFunctionToPend,pvParameter1,ulParameter2,ret) CAN_TI2R_TXRQ_Pos (0U)ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)ServicerDebugAccessorCAN_ESR_BOFF CAN_ESR_BOFF_MskGPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)CAN_FA1R_FACT11 CAN_FA1R_FACT11_MskTIM_CR2_CCPC_Pos (0U)GPIO_AFRL_AFSEL4_3 0x00080000UDBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_MskSCB_SHCSR_USGFAULTPENDED_Pos 12UIS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM11))PreemptPriorityBitsDAC_CR_DMAUDRIE1_Pos (13U)CAN_F4R1_FB9 CAN_F4R1_FB9_MskCAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_MskCAN_F3R2_FB9 CAN_F3R2_FB9_MskRCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_MskFSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)__O volatileETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)ADC_SQR3_SQ2 ADC_SQR3_SQ2_MskTPI_DEVID_AsynClkIn_Pos 5UCONTROL_SPSEL_Pos 1UDCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)CAN_F9R1_FB14 CAN_F9R1_FB14_MskUSB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)SDIO_RESP4_CARDSTATUS4_Pos (0U)PROCESS_BITS(target) "and r1, %[C0], r1, lsr %[Pos]\n\t" "and r2, %[C0], r2, lsr %[Pos]\n\t" "orr r1, r1, r1, lsr #15\n\t" "orr r1, r1, r2, lsl #2\n\t" "and r3, %[C0], r3, lsr %[Pos]\n\t" "orr r2, r2, r3, lsl #17\n\t" "orr " target ", r2, r3, lsl #2\n\t" "bfi " target ", r1, #0, #3\n\t"GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_MskCAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)ADC_JSQR_JSQ1_Pos (0U)FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)CAN_FS1R_FSC19 CAN_FS1R_FSC19_MskETH_DMASR_MMCS_Pos (27U)CAN_F6R2_FB0 CAN_F6R2_FB0_MskCAN_F6R2_FB30_Pos (30U)DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk__NEWLIB__ 4ETH_MACCR_BL_8 0x00000020UDMA_SxCR_CT_Pos (19U)LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)CAN_F12R1_FB24_Pos (24U)GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1GPIO_OSPEEDR_OSPEED6_1 0x00002000UCAN_F10R1_FB31_Pos (31U)LL_DMA_SetDataLength__cpp_decltype_auto 201304LFSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_MskCAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)INTPTR_MIN (-INTPTR_MAX - 1)CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)__cpp_capture_star_this 201603LFLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)CAN_F8R2_FB17_Pos (17U)CAN_F0R1_FB13_Pos (13U)USART_CR3_EIE_Pos (0U)CAN_TDL0R_DATA2_Pos (16U)ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_MskCAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)RTC_BKP15R RTC_BKP15R_MskETH_DMASR_TBUS ETH_DMASR_TBUS_MskEXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)CAN_F12R1_FB18_Pos (18U)GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_MskRCC_IRQnI2C_CR1_ALERT_Pos (13U)TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0__CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)SCB_CFSR_MEMFAULTSR_Pos 0UI2C_SR2_GENCALL I2C_SR2_GENCALL_MskCAN_F0R1_FB30_Pos (30U)CAN_BTR_BRP CAN_BTR_BRP_MskCAN_F0R2_FB30_Pos (30U)CAN_F5R1_FB31 CAN_F5R1_FB31_MskTIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)CAN_F11R2_FB10_Pos (10U)_GLIBCXX_MAX_SIZE_TYPE_H 1__STATIC_INLINE static inlineCAN_F1R1_FB2_Pos (2U)DMA_HISR_TEIF5_Pos (9U)CAN_FM1R_FBM CAN_FM1R_FBM_MskFSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_MskUSB_OTG_DOEPCTL_MPSIZ_Pos (0U)ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)ETH_MACFFR_DAIF_Pos (3U)RTC_ALRMAR_HT RTC_ALRMAR_HT_MskFSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)CAN_TSR_TME0 CAN_TSR_TME0_MskFSMC_SR2_IFS FSMC_SR2_IFS_MskCAN_F0R1_FB24_Pos (24U)vSemaphoreDelete(xSemaphore) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )CAN_F10R1_FB17 CAN_F10R1_FB17_Msk__LONG_LONG_MAX__ 0x7fffffffffffffffLLTIM10 ((TIM_TypeDef *) TIM10_BASE)SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_MskSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)FLASH_SR_EOP FLASH_SR_EOP_MsktskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )NVIC_SRV_RX_IRQ_NAME DMA2_Stream1_IRQntraceQUEUE_CREATE_FAILED(ucQueueType) GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)BusFault_IRQnTIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_MskLL_DMA_MODE_NORMAL 0x00000000UCAN_F3R1_FB0 CAN_F3R1_FB0_MskFSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)__IMPORT ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)DCMI_ESUR_LSU_Pos (8U)CAN_F8R1_FB27 CAN_F8R1_FB27_MskITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)OTYPERETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_MskCAN_F11R2_FB5 CAN_F11R2_FB5_MskCAN_F1R1_FB22 CAN_F1R1_FB22_MskCAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)CoreDebug_DEMCR_VC_STATERR_Pos 7UpdFREERTOS_ERRNO_EILSEQ 138SYSCFG_EXTICR3_EXTI9_Pos (4U)CAN_F10R1_FB16 CAN_F10R1_FB16_MskGPIO_OSPEEDR_OSPEED3 0x000000C0UFSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)CAN_FM1R_FBM13 CAN_FM1R_FBM13_MskCAN_MSR_WKUI CAN_MSR_WKUI_MskMatrixFSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)SPI_CR2_SSOE SPI_CR2_SSOE_MskGPIO_MODER_MODER9_Pos (18U)CAN_F12R2_FB3 CAN_F12R2_FB3_MskSYSCFG_EXTICR1_EXTI0_PE 0x00000004URTC_ISR_INITF RTC_ISR_INITF_MskCAN_F13R2_FB14_Pos (14U)ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)USART_CR1_UE_Pos (13U)CAN_F13R2_FB23 CAN_F13R2_FB23_MskvPortSVCHandler SVC_HandlerGPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)CAN_F3R2_FB9_Pos (9U)USART_CR2_CPHA_Pos (9U)CAN_F1R2_FB2 CAN_F1R2_FB2_MskCAN_FM1R_FBM6_Pos (6U)xQueueSendToFront(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )EXTI3_IRQn__STM32F2xx_LL_GPIO_H CAN_F4R1_FB5 CAN_F4R1_FB5_MskETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)CAN_F9R2_FB19_Pos (19U)USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)FSMC_SR3_IREN FSMC_SR3_IREN_MskCAN_F4R1_FB18 CAN_F4R1_FB18_MskDCMI_IER_ERR_IE_Pos (2U)ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)CAN_FS1R_FSC20_Pos (20U)CAN_F2R1_FB28_Pos (28U)DMA_SxNDT_Pos (0U)TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)CAN_F10R2_FB24 CAN_F10R2_FB24_MskI2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)_svramFSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)LL_DMA_WriteReg(__INSTANCE__,__REG__,__VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))RCC_CIR_PLLI2SRDYIE_Pos (13U)ETH_DMASR_EBS_ReadTransf_Pos (24U)CAN_F1R1_FB4 CAN_F1R1_FB4_MskUSB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_MskDCMI_ESCR_LSC DCMI_ESCR_LSC_MskCAN_F1R2_FB20_Pos (20U)CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)CAN_F0R2_FB4 CAN_F0R2_FB4_MskpdFREERTOS_ERRNO_EALREADY 120TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)TIM_DIER_TDE TIM_DIER_TDE_MskRCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)CoreDebug_DHCSR_DBGKEY_Pos 16U_Alignas(x) alignas(x)USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_MskUSART1_IRQnCAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)ETH_DMABMR_DA_Pos (1U)USB_OTG_HCINTMSK_DTERRM_Pos (10U)CAN_F12R1_FB28 CAN_F12R1_FB28_MskFSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)TIM_SR_CC2OF TIM_SR_CC2OF_MskRCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_MskqueueQUEUE_TYPE_BASE ( ( uint8_t ) 0U )FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_MskFSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)DWT_CTRL_NOTRCPKT_Pos 27URTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)CAN_MCR_TTCM_Pos (7U)LL_DMA_STREAM_6 0x00000006UFSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)CAN_F1R2_FB14_Pos (14U)GPIO_IDR_IDR_8 GPIO_IDR_ID8TAFCRFSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)CAN_ESR_REC CAN_ESR_REC_MskDWT_CTRL_CYCCNTENA_Pos 0UTIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)CAN_TSR_TME CAN_TSR_TME_MskCAN_F3R2_FB30_Pos (30U)RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)USB_OTG_GOTGINT_HNGDET_Pos (17U)_SYS_FEATURES_H __WCHAR_MIN__ 0UCAN_F12R2_FB13 CAN_F12R2_FB13_MskGPIO_OTYPER_OT_14 GPIO_OTYPER_OT14portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)vTaskNotifyGiveFromISR(xTaskToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) );DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_MskADC_SQR3_SQ6 ADC_SQR3_SQ6_MskCAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)CAN_F5R2_FB23 CAN_F5R2_FB23_Msk_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)FSMC_BCR1_MTYP_Pos (2U)GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)GPIO_PUPDR_PUPD0_1 0x00000002UETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)ADC_CSR_DOVR3 ADC_CSR_OVR3SDIO_STA_TXDAVL_Pos (20U)LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000UCAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_MskCAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1CAN_RI1R_STID_Pos (21U)GPIO_OTYPER_OT3 0x00000008UI2C_SR2_SMBDEFAULT_Pos (5U)LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_MskCAN_F9R1_FB26 CAN_F9R1_FB26_MskETH_MACA3HR_MBC_LBits31_24 0x08000000UDMA_LISR_HTIF2 DMA_LISR_HTIF2_MskI2C_SR2_MSL_Pos (0U)CAN_FS1R_FSC13_Pos (13U)CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_MskFSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)CAN_F13R1_FB3 CAN_F13R1_FB3_MskETH_DMAOMR_FTF ETH_DMAOMR_FTF_MskCAN_F3R2_FB18_Pos (18U)SDIO_MASK_CMDRENDIE_Pos (6U)__INT_LEAST64_MAX__ 0x7fffffffffffffffLLUSB_OTG_GINTMSK_IEPINT_Pos (18U)ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)RTC_ALRMAR_HU RTC_ALRMAR_HU_MskCAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_MskCAN_F8R1_FB12_Pos (12U)DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)pcReadFromtskDEFAULT_INDEX_TO_NOTIFY ( 0 )__glibcxx_constexpr_assert(cond) if (std::__is_constant_evaluated() && !bool(cond)) __builtin_unreachable()ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)GPIO_AFRL_AFSEL1_0 0x00000010UGPIO_MODER_MODE0 0x00000003UUSB_OTG_DAINT_OEPINT_Pos (16U)RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)USB_OTG_GAHBCFG_TXFELVL_Pos (7U)CAN_F8R2_FB21_Pos (21U)USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)RCC_CR_HSION_Pos (0U)ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_MskCAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)configSUPPORT_DYNAMIC_ALLOCATION 0RCC_CIR_HSIRDYC_Pos (18U)FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)CAN_F10R1_FB30 CAN_F10R1_FB30_MskEXTI_EMR_EM21 EXTI_EMR_MR21FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL )ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)CAN_F5R1_FB17 CAN_F5R1_FB17_MskSYSCFG_EXTICR2_EXTI7_PH 0x00007000URCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_MskFSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)_GLIBCXX_USE_ST_MTIM 1CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)CAN_F13R1_FB24 CAN_F13R1_FB24_MskCAN_FA1R_FACT7_Pos (7U)FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_MskADC_SMPR1_SMP14_Pos (12U)CAN_TDL2R_DATA3_Pos (24U)_ATFILE_SOURCEADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)queueQUEUE_TYPE_SET ( ( uint8_t ) 0U )semGIVE_BLOCK_TIME ( ( TickType_t ) 0U )USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)__alloc_size2(n,x) __attribute__((__alloc_size__(n, x)))_SIZET_ listLIST_IS_EMPTY(pxList) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )TIM_CCER_CC3NE TIM_CCER_CC3NE_MskDMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKCAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_MskRTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)GPIOB ((GPIO_TypeDef *) GPIOB_BASE)CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)_GLIBCXX_SIZE_T_IS_UINT 1LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)ETH_MMCCR_CSR_Pos (1U)LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBENADC_JDR1_JDATA ADC_JDR1_JDATA_MskDMA_HISR_FEIF5 DMA_HISR_FEIF5_MskportRECORD_READY_PRIORITY(uxPriority,uxReadyPriorities) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)traceTASK_RESUME(pxTaskToResume) USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)ulTaskNotifyTake(xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )TIM_BDTR_OSSR TIM_BDTR_OSSR_MskDMA_LISR_TCIF1_Pos (11U)ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)USB_OTG_HCSPLT_XACTPOS_Pos (14U)CAN_F12R2_FB0_Pos (0U)__ASM __asmCAN_IER_FFIE1_Pos (5U)ETH_MMCCR_MCF_Pos (3U)portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_MskGPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)__SCHAR_WIDTH__ 8CAN_F13R1_FB27 CAN_F13R1_FB27_MskGPIO_IDR_IDR_15 GPIO_IDR_ID15CAN_F12R1_FB2 CAN_F12R1_FB2_MskEXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_MskUSB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_MskADC_SMPR2_SMP3_Pos (9U)ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_MskFLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)xTaskNotify(xTaskToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0CAN_F6R2_FB22 CAN_F6R2_FB22_MskI2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk_RAND48_SEED_0 (0x330e)CAN_F0R2_FB27 CAN_F0R2_FB27_MskCAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)FSMC_SR2_IREN_Pos (3U)FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)SYSCFG_EXTICR3_EXTI11_PA 0x00000000ULL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPENCAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)CAN_F4R1_FB3 CAN_F4R1_FB3_MskGPIO_AFRH_AFSEL11_3 0x00008000UUSB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)CAN_F12R2_FB18_Pos (18U)CAN_F10R2_FB25_Pos (25U)__UINTMAX_C(c) c ## ULLCAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)ETH_PTPTTLR_TTSL_Pos (0U)USB_OTG_GINTSTS_GINAKEFF_Pos (6U)ETH_DMASR_ERS ETH_DMASR_ERS_MskDAC_CR_WAVE2 DAC_CR_WAVE2_MskUSB_OTG_HCTSIZ_DPID_Pos (29U)CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)LL_TIM_ReadReg(__INSTANCE__,__REG__) READ_REG((__INSTANCE__)->__REG__)xPSR_T_Pos 24UEXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)CAN_MCR_RESET_Pos (15U)UART5 ((USART_TypeDef *) UART5_BASE)DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)WINT_MAXARM_MPU_CACHEP_WB_WRA 1UTIM_CCER_CC2NP_Pos (7U)GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)_GLIBCXX_USE_ALLOCATOR_NEW 1RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk__PACKED_UNION union __attribute__((packed, aligned(1)))CAN_F9R2_FB18 CAN_F9R2_FB18_MskCAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_MskCAN_F2R2_FB13 CAN_F2R2_FB13_MskDAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_MskTIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5ENRTC_CR_OSEL RTC_CR_OSEL_MskDAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)TypeResetLL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)LL_GPIO_InitTIM_CR1_UDIS_Pos (1U)ETH_MACCR_IFG_Pos (17U)DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_MskCAN_F1R1_FB17 CAN_F1R1_FB17_MskTIM_RCR_REP_Pos (0U)__ATTRIBUTE_IMPURE_DATA__ FSMC_PMEM3_MEMWAIT3_Pos (8U)TIM_DIER_UDE_Pos (8U)TPI_SPPR_TXMODE_Pos 0UTIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_MskFSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)ETH_MACDBGR_MMTEA_Pos (16U)AHB1RSTRDBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_MskCAN_F0R2_FB18_Pos (18U)GPIO_AFRL_AFSEL0 0x0000000FUTIM8_BRK_TIM12_IRQnUSB_OTG_DOEPCTL_EPTYP_Pos (18U)FSMC_PCR4_TAR_Pos (13U)configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)pdFREERTOS_ERRNO_EINPROGRESS 119__LLACCUM_FBIT__ 31ETH_MACCR_LM ETH_MACCR_LM_MskSYSCFG_EXTICR4_EXTI13_PF 0x00000050UCAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)GPIO_PUPDR_PUPD1 0x0000000CUINT_LEAST64_MAX __INT_LEAST64_MAX__DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)_FVWRITE_IN_STREAMIO 1ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_MskRCC_APB2LPENR_SDIOLPEN_Pos (11U)GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)RTC_ISR_TSF RTC_ISR_TSF_MskSCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)GNU C++20 13.3.1 20240614 -mthumb -mfloat-abi=soft -mcpu=cortex-m3 -march=armv7-m -ggdb3 -O3 -O2 -std=gnu++20 -ffreestanding -fbuiltin -fno-exceptions -fno-rtti -fno-threadsafe-staticsTIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)StaticList_tADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)DMA_LIFCR_CDMEIF2_Pos (18U)RCC_APB2LPENR_SPI1LPEN_Pos (12U)CAN_F3R1_FB13_Pos (13U)USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)I2C_SR1_ARLO_Pos (9U)GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)GPIO_BSRR_BS_2 GPIO_BSRR_BS2USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)CAN_F2R2_FB28_Pos (28U)FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk__cust_imoveUSB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xfCAN_FA1R_FACT17_Pos (17U)IWDG_SR_PVU_Pos (0U)RNG_SR_SEIS RNG_SR_SEIS_Msk__STM32F2xx_LL_CORTEX_H FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)USB_OTG_DIEPCTL_NAKSTS_Pos (17U)USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_MskUSB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)CAN_F12R2_FB3_Pos (3U)GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4__FLT32X_EPSILON__ 2.2204460492503131e-16F32xSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)CAN_F5R1_FB24 CAN_F5R1_FB24_MskADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)TPI_DEVID_MANCVALID_Pos 10UCAN_F8R2_FB7_Pos (7U)xQueueOverwrite(xQueue,pvItemToQueue) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1CAN_F13R2_FB7 CAN_F13R2_FB7_MskSDIO_ARG_CMDARG SDIO_ARG_CMDARG_MskEXTI_SWIER_SWIER1_Pos (1U)RTC_DR_WDU_Pos (13U)GPIO_BSRR_BS_6 GPIO_BSRR_BS6ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_MskSCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)CAN_TI1R_EXID CAN_TI1R_EXID_MskRCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_MskRTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_MskFSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)CAN_F9R1_FB7 CAN_F9R1_FB7_MskLL_SYSCFG_EXTI_PORTI (uint32_t)8FSMC_BCR3_WAITEN_Pos (13U)EXTI_IMR_MR14 EXTI_IMR_MR14_MskUSB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_MskCAN_F11R2_FB26 CAN_F11R2_FB26_MskRCC_CFGR_MCO1 RCC_CFGR_MCO1_MskFSMC_PATT4_ATTSET4_Pos (0U)EXTI_FTSR_TR3_Pos (3U)FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)FLASH_OPTCR_nWRP_3 (0x008UL << FLASH_OPTCR_nWRP_Pos)DMA_LISR_TEIF1 DMA_LISR_TEIF1_MskETH_MMCCR_ROR ETH_MMCCR_ROR_MskCAN_F8R1_FB15 CAN_F8R1_FB15_MskportINLINE __inlineCAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)DWT_CPICNT_CPICNT_Pos 0ULL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)SYSCFG_EXTICR4_EXTI15_PF 0x00005000UCoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8DCMI_SR_VSYNC_Pos (1U)FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_MskFSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)ADC_CSR_STRT2 ADC_CSR_STRT2_MskCAN_F7R1_FB10 CAN_F7R1_FB10_MskADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)CAN_F1R1_FB15 CAN_F1R1_FB15_MskFSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)USART2_BASE (APB1PERIPH_BASE + 0x4400UL)RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_MskCAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)CAN_F7R2_FB9 CAN_F7R2_FB9_MskI2C_CR1_SWRST_Pos (15U)CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)SYSCFG_EXTICR4_EXTI15_PC 0x00002000UUSB_OTG_NPTXFD_Pos (16U)CAN_F6R2_FB6 CAN_F6R2_FB6_MskRTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)FLASH_SR_SOP_Pos (1U)FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)USB_OTG_TX0FSA_Pos (0U)ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)UID_BASE 0x1FFF7A10ULCAN_F13R2_FB15 CAN_F13R2_FB15_MskCAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_MskUSB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_MskSDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)pcTimerGetTimerName pcTimerGetNameUSB_OTG_GCCFG_SOFOUTEN_Pos (20U)SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk__cpp_lib_move_iterator_concept 202207LUSB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3FSMC_BCR3_FACCEN_Pos (6U)CAN_F4R2_FB0_Pos (0U)CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)ETH_MACFCR_PLT ETH_MACFCR_PLT_MskDMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_MskSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)GPIO_OTYPER_OT5 0x00000020UDCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_MskFSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)EXTI_FTSR_TR2 EXTI_FTSR_TR2_MskRCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)CAN_F10R2_FB16 CAN_F10R2_FB16_MskxPSR_N_Pos 31U_REENT_INIT_RESERVED_1 CAN_F12R1_FB13_Pos (13U)CAN_F10R1_FB20_Pos (20U)GPIO_BSRR_BS_14 GPIO_BSRR_BS14USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)PWR_CR_PVDE_Pos (4U)USART_SR_ORE_Pos (3U)USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)TIM_CR1_CMS_Pos (5U)CAN_F9R2_FB16_Pos (16U)GPIO_AFRH_AFSEL10 0x00000F00UUSB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_MskSPI_DR_DR_Pos (0U)ADC_JSQR_JL_Pos (20U)__VERSION__ "13.3.1 20240614"__lock_init(lock) __retarget_lock_init(&lock)FSMC_SR2_ILEN FSMC_SR2_ILEN_MskRCC_AHB1ENR_ETHMACTXEN_Pos (26U)xListItem ListItem_tCAN_TDT0R_TGT_Pos (8U)ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)SCB_DFSR_HALTED_Msk (1UL )EXTI_PR_PR19_Pos (19U)CAN_F2R2_FB20 CAN_F2R2_FB20_MskCAN_RF1R_FULL1 CAN_RF1R_FULL1_MskUSB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)CAN_F6R2_FB13_Pos (13U)EXTI_IMR_MR22_Pos (22U)CAN_TSR_ALST0_Pos (2U)ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)GPIO_LCKR_LCK7_Pos (7U)I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)CAN_FS1R_FSC24 CAN_FS1R_FSC24_MskEXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1WINT_MIN__FRACT_EPSILON__ 0x1P-15REXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)_GLIBCXX_END_NAMESPACE_ALGO CAN_FM1R_FBM8 CAN_FM1R_FBM8_MskUINT_LEAST8_MAX__CMSIS_COMPILER_H USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_MskCAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)LL_TIM_SR_CC4OF TIM_SR_CC4OFCAN_F6R1_FB23 CAN_F6R1_FB23_MskDCMI_ESCR_LEC DCMI_ESCR_LEC_MskDAC_CR_DMAEN2_Pos (28U)__UINT_LEAST16_MAX__ 0xffffETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)CAN_F0R1_FB28 CAN_F0R1_FB28_MskETH_MACMIIAR_MR ETH_MACMIIAR_MR_MskUSB_OTG_HCSPLT_COMPLSPLT_Pos (16U)DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)CAN_F9R2_FB1_Pos (1U)USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))UART_Af LL_GPIO_AF_8RTC_ALRMAR_MSK1_Pos (7U)EXTI_IMR_MR16_Pos (16U)RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)MatrixBitLookupTable<0>configUSE_TIMERS 0RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_MskLL_MPU_REGION_NUMBER1 0x01U__size_t__ CAN_F7R1_FB0 CAN_F7R1_FB0_MskSCB_CFSR_IACCVIOL_Msk (1UL )USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_MskRTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)GPIO_AFRL_AFSEL6_3 0x08000000UCAN_F8R2_FB23_Pos (23U)CAN_F8R1_FB8_Pos (8U)CAN_TSR_ABRQ1_Pos (15U)_GLIBCXX11_USE_C99_STDIO 1I2C_SR1_BERR I2C_SR1_BERR_MskGPIO_MODER_MODER7 GPIO_MODER_MODER7_MskGPIO_AFRH_AFSEL14_3 0x08000000UPWR_CR_PLS_Pos (5U)CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_MskI2C_SR1_PECERR I2C_SR1_PECERR_MskSCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )SYSCFG_EXTICR1_EXTI3_PB 0x00001000UUSB_OTG_GINTSTS_OEPINT_Pos (19U)CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)ADC_CSR_OVR2 ADC_CSR_OVR2_MskRCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)RCC_PLLCFGR_PLLSRC_HSI 0x00000000U_GLIBCXX_PURE __attribute__ ((__pure__))ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)CAN_F9R1_FB19 CAN_F9R1_FB19_MskTIM8 ((TIM_TypeDef *) TIM8_BASE)ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)MatrixBitLookupTable<1>CAN_FFA1R_FFA1_Pos (1U)FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)CAN_F11R1_FB27 CAN_F11R1_FB27_MskCAN_F2R1_FB14 CAN_F2R1_FB14_MskCAN_FM1R_FBM0 CAN_FM1R_FBM0_MskUSB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_MskUSB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)errQUEUE_FULL ( ( BaseType_t ) 0 )RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)FSMC_BTR3_DATAST FSMC_BTR3_DATAST_MskTPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)LL_GPIO_AF_13 (0x000000DU)RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)CAN_F5R2_FB2 CAN_F5R2_FB2_MskCAN_F2R2_FB11_Pos (11U)EXTI_RTSR_TR18_Pos (18U)SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)__cpp_deduction_guides 201907LADC_CSR_JSTRT1_Pos (3U)DFSRCAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)ADC_SR_OVR_Pos (5U)_PSTL_PRAGMA_DECLARE_REDUCTION(NAME,OP) _PSTL_PRAGMA(omp declare reduction(NAME:OP : omp_out(omp_in)) initializer(omp_priv = omp_orig))RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_MskRCC_APB2LPENR_TIM10LPEN_Pos (17U)CAN_F2R1_FB23_Pos (23U)GPIO_MODER_MODE6 0x00003000UCAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)CAN_F11R1_FB23_Pos (23U)CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)ADC_CCR_DDS_Pos (13U)USB_OTG_DTHRCTL_ARPEN_Pos (27U)CAN_FM1R_FBM4_Pos (4U)__INT_LEAST64_TYPE__ long long intMPU_TYPE_DREGION_Pos 8UUSB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)_T_SIZE_ GPIO_AFRH_AFSEL9_0 0x00000010UCAN_F10R2_FB5 CAN_F10R2_FB5_MskLL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)_GLIBCXX_FORWARD(_Tp,__val) std::forward<_Tp>(__val)DAC_CR_EN2_Pos (16U)USART6 ((USART_TypeDef *) USART6_BASE)WWDG_CFR_W4 WWDG_CFR_W_4ETH_MACA1HR_MBC ETH_MACA1HR_MBC_MskRCC_APB2LPENR_USART6LPEN_Pos (5U)AHB1LPENRFSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_MskCAN_F4R2_FB4 CAN_F4R2_FB4_MskRCC_AHB1RSTR_DMA2RST_Pos (22U)RCC_AHB1ENR_GPIOEEN_Pos (4U)TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)listSET_LIST_INTEGRITY_CHECK_1_VALUE(pxList) CAN_F2R1_FB17_Pos (17U)ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_MskCAN_F10R1_FB22 CAN_F10R1_FB22_MskRCC_BDCR_BDRST RCC_BDCR_BDRST_MskRCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_MskCAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)SCB_SCR_SEVONPEND_Pos 4UDMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)CAN_F13R1_FB16 CAN_F13R1_FB16_MskFSMC_BWTR4_BUSTURN_Pos (16U)CAN_F13R1_FB6 CAN_F13R1_FB6_MskSYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_MskportYIELD_WITHIN_API portYIELDDCMI_CR_CM_Pos (1U)__bool_true_false_are_defined 1CAN_F4R1_FB1_Pos (1U)USB_OTG_GINTSTS_ENUMDNE_Pos (13U)RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)CAN_F13R2_FB20_Pos (20U)DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)SDIO_DTIMER_DATATIME_Pos (0U)USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)RCC_CSR_WWDGRSTF_Pos (30U)ADC_CR1_EOCIE_Pos (5U)EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)TIM_CCMR1_IC2F TIM_CCMR1_IC2F_MskTIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)CAN_F3R2_FB7 CAN_F3R2_FB7_MskLL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_MskSYSCFG_EXTICR4_EXTI14_PD 0x00000300UGPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk_GLIBCXX_HAVE_FLOORF 1ADC_CR1_DISCEN_Pos (11U)CAN_F4R2_FB29 CAN_F4R2_FB29_MskCAN_FFA1R_FFA25_Pos (25U)RCC_APB1ENR_PWREN_Pos (28U)SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_MskEspCrashedFSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)CAN_F4R1_FB27_Pos (27U)DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)__SYS_CONFIG_H__ CAN_F7R1_FB0_Pos (0U)CAN_FS1R_FSC1_Pos (1U)CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)DWT_FUNCTION_FUNCTION_Msk (0xFUL )ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)I2C_CR2_FREQ I2C_CR2_FREQ_MskDWT_FUNCTION_FUNCTION_Pos 0URCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)ETH_MACFCR_PT ETH_MACFCR_PT_MskEXTI_SWIER_SWIER14_Pos (14U)CAN_F12R1_FB11 CAN_F12R1_FB11_MskWWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1DCMI_SR_HSYNC DCMI_SR_HSYNC_MskGPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)RTC_TR_MNT RTC_TR_MNT_MskETH_MACPMTCSR_PD_Pos (0U)FLASH_OPTCR_BOR_LEV_0 0x00000004UGPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)CAN_F10R2_FB4_Pos (4U)DAC_CR_DMAEN1_Pos (12U)CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_MskCAN_F12R2_FB8 CAN_F12R2_FB8_MskEXTI_PR_PR19 EXTI_PR_PR19_MskFSMC_PCR4_ECCEN_Pos (6U)FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)CAN_F6R2_FB15 CAN_F6R2_FB15_MskCAN_F6R2_FB8_Pos (8U)CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_MskCAN_F3R2_FB13_Pos (13U)ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)DCMI_ICR_ERR_ISC_Pos (2U)INT_FAST8_MINxStreamBufferCreate(xBufferSizeBytes,xTriggerLevelBytes) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)CAN_F9R1_FB24_Pos (24U)CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)USART_CR3_IRLP USART_CR3_IRLP_MskETH_MACDBGR_RFFL_FULL_Pos (8U)RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)RTC_ALRMAR_MNU RTC_ALRMAR_MNU_MskFSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)__need_wchar_t__UINT32_TYPE__ long unsigned intCAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_MskUSART_CR2_CLKEN_Pos (11U)_GLIBCXX_CPU_DEFINES 1CAN_F13R2_FB3_Pos (3U)__UFRACT_MIN__ 0.0URDWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_MskCAN_F9R2_FB7_Pos (7U)RCC_CIR_CSSF_Pos (7U)CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)TIM_CR2_OIS2N TIM_CR2_OIS2N_MskCAN_F0R1_FB6 CAN_F0R1_FB6_MsktracePOST_MOVED_TASK_TO_READY_STATE(pxTCB) traceEVENT_GROUP_SYNC_BLOCK(xEventGroup,uxBitsToSet,uxBitsToWaitFor) ARM_MPU_RASR(DisableExec,AccessPermission,TypeExtField,IsShareable,IsCacheable,IsBufferable,SubRegionDisable,Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)EXTI_FTSR_TR11_Pos (11U)CAN_F5R2_FB23_Pos (23U)TIM_CR2_OIS1N_Pos (9U)CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_MskRCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_MskCAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_MskGPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5USART_CR2_STOP USART_CR2_STOP_MskFSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_MskTIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)RTC_CR_COE_Pos (23U)CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)CAN_F13R2_FB6_Pos (6U)CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk__SIZE_WIDTH__ 32USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_MskI2C_SR1_TXE_Pos (7U)GPIO_IDR_ID11 0x00000800UGPIO_MODER_MODE9_1 0x00080000UUINT16_MAXCAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)SDIO_MASK_RXACTIE_Pos (13U)IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2) || ((INSTANCE) == I2C3))CAN_F5R2_FB17_Pos (17U)MPU_RASR_ATTRS_Pos 16UDMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)USART_CR1_OVER8_Pos (15U)LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)GPIO_ODR_ODR_8 GPIO_ODR_OD8__cpp_conditional_explicit 201806LGPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)CAN_F2R2_FB1_Pos (1U)RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)ETH_PTPSSIR_STSSI_Pos (0U)__cpp_lib_hardware_interference_size 201703LADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)CAN_F2R1_FB21 CAN_F2R1_FB21_MskUSB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk11ErrorStatusUSB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)SCB_SHCSR_MONITORACT_Pos 8UEXTI_EMR_EM2 EXTI_EMR_MR2USB_OTG_HFIR_FRIVL_Pos (0U)GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1SYSCFG_EXTICR2_EXTI6_PB 0x00000100UFSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)CAN_F5R2_FB28 CAN_F5R2_FB28_MskRTC_BKP13R_Pos (0U)RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)USB_OTG_GOTGCTL_SRQ_Pos (1U)__cpp_lib_is_swappable 201603LUSB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)LL_DMA_SetMode__cmp_custADC_CR1_SCAN_Pos (8U)USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk_ZN5crash6Matrix5colorEttCAN_FMR_CAN2SB_Pos (8U)RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk__sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)INT8_MAX __INT8_MAX__CAN_RI0R_EXID CAN_RI0R_EXID_MskARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)ETH_MACCR_IFG ETH_MACCR_IFG_MskCAN_F11R1_FB28_Pos (28U)FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)__INLINE inlineCoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)TimeStatusGPIO_MODER_MODE8_0 0x00010000USCB_CFSR_MEMFAULTSR_Msk (0xFFUL )EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)SDIO_STA_RXDAVL_Pos (21U)CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)__ARM_ARCH_PROFILECAN_F10R2_FB20_Pos (20U)DWT_FOLDCNT_FOLDCNT_Pos 0UGPIO_BSRR_BS_15 GPIO_BSRR_BS15RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)FSMC_SR2_IFEN_Pos (5U)EXTI_PR_PR7_Pos (7U)GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3PWR_CR_CWUF PWR_CR_CWUF_MskEXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0)I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)SCB_SCR_SLEEPONEXIT_Pos 1UCAN_F7R2_FB14 CAN_F7R2_FB14_MskCAN_F1R2_FB19 CAN_F1R2_FB19_Msk__builtin_memsetCAN_F0R2_FB8 CAN_F0R2_FB8_MskCAN_F10R1_FB4 CAN_F10R1_FB4_MskETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_MskTIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)ADC_JOFR2_JOFFSET2_Pos (0U)CAN_MSR_RX_Pos (11U)FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)CAN_F6R1_FB8_Pos (8U)CAN_F10R1_FB5_Pos (5U)ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)USB_OTG_GOTGCTL_BSVLD_Pos (19U)BKP12RRTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)CAN_F6R1_FB9_Pos (9U)CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)_EXT_NUMERIC_TRAITS 1USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_MskUSB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)_GLIBCXX_HAVE_MEMORY_H 1CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)CAN_F12R2_FB30_Pos (30U)CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)configUSE_IDLE_HOOK 0LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)taskEXIT_CRITICAL_FROM_ISR(x) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_MskCAN_F4R1_FB21_Pos (21U)FSMC_SR2_ILEN_Pos (4U)EXTI_IMR_IM13 EXTI_IMR_MR13ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)__SCCSID(s) struct __hackTPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)IncrementModeETH_MACCR_APCS ETH_MACCR_APCS_MskTIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)GPIO_AFRL_AFSEL3 0x0000F000ULL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)CAN_F13R1_FB4_Pos (4U)CAN_RF0R_FMP0_Pos (0U)I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)portMAX_DELAY ( TickType_t ) 0xffffffffULCAN_F3R2_FB5 CAN_F3R2_FB5_MskDMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)USB_OTG_DIEPINT_INEPNM_Pos (5U)CAN_F9R1_FB8_Pos (8U)RTC_TSTR_MNT RTC_TSTR_MNT_MskUSART_CR1_SBK_Pos (0U)__cpp_using_enum 201907LCAN_F12R2_FB24_Pos (24U)RTC_ALRMAR_SU_Pos (0U)DCMI_ICR_FRAME_ISC_Pos (0U)CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)EXTI15_10_IRQnRCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)RCC_CR_PLLON_Pos (24U)RCC_AHB1ENR_GPIOBEN_Pos (1U)DMA_LISR_TEIF1_Pos (9U)FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)_RANGES_UTIL_H 1EXTI_IMR_IM17 EXTI_IMR_MR17StaticMiniListItem_tCAN_TDT0R_TIME_Pos (16U)ETH_MACFFR_SAIF ETH_MACFFR_SAIF_MskARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)TIM_CR1_CEN TIM_CR1_CEN_MskFLASH_SR_PGAERR FLASH_SR_PGAERR_MskRTC_TSTR_PM_Pos (22U)ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MISIS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8))ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)xSTATIC_LIST_ITEMWCHAR_MAXDMA_SxNDT DMA_SxNDT_MskBKP13RUSB_OTG_DEVICE_BASE 0x800ULETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)__FBSDID(s) struct __hackLL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF__UINT_LEAST8_MAX__ 0xffCoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)USB_OTG_GOTGCTL_DBCT_Pos (17U)RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_MskADC3_BASE (APB2PERIPH_BASE + 0x2200UL)GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)GPIO_MODER_MODER10 GPIO_MODER_MODER10_MskDMA_HISR_FEIF5_Pos (6U)CAN_IER_FOVIE1 CAN_IER_FOVIE1_MskCAN_F3R1_FB20 CAN_F3R1_FB20_MskCAN_F12R1_FB7 CAN_F12R1_FB7_MskFSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_MskCAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)SDIO_RESP0_CARDSTATUS0_Pos (0U)DMA_LIFCR_CTCIF1_Pos (11U)DMA_SxPAR_PA DMA_SxPAR_PA_MskEXTI_IMR_MR20 EXTI_IMR_MR20_MskRCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_MskINTPTR_MAX __INTPTR_MAX__ETH_DMARPDR_RPD_Pos (0U)FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)PWR ((PWR_TypeDef *) PWR_BASE)CAN_F2R1_FB2_Pos (2U)CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk__FLT64_IS_IEC_60559__ 1RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_MskUSB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_MskRTC_CR_ALRBIE RTC_CR_ALRBIE_MskFSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_MskDMA_HISR_TCIF4_Pos (5U)USB_OTG_HCINTMSK_AHBERR_Pos (2U)CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)FSMC_BWTR2_BUSTURN_Pos (16U)CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10ENLL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6ENSDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_MskCAN_TSR_LOW0_Pos (29U)DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_MskCAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)ETH_MACFCR_FCBBPA_Pos (0U)TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_MskUSB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_MskETH_MMCRIR_RFAES_Pos (6U)LL_DMA_FIFOMODE_DISABLE 0x00000000UTIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)CAN_IER_LECIE_Pos (11U)SYSCFG_EXTICR4_EXTI13_PD 0x00000030UCAN_FS1R_FSC16 CAN_FS1R_FSC16_MskFSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_MskAPB1LPENRCAN_F5R1_FB1_Pos (1U)FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)CAN_F6R1_FB16 CAN_F6R1_FB16_MskxStreamBufferCreateStatic(xBufferSizeBytes,xTriggerLevelBytes,pucStreamBufferStorageArea,pxStaticStreamBuffer) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )FSMC_BCR4_ASYNCWAIT_Pos (15U)CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)USART_CR2_ADD USART_CR2_ADD_MskCAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)SYSCFG_EXTICR2_EXTI4_PF 0x00000005URTC_TSDR_MU RTC_TSDR_MU_MskUSB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_MskEXTI_EMR_MR11 EXTI_EMR_MR11_MskETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)LL_TIM_OCIDLESTATE_LOW 0x00000000UUSB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)portPOINTER_SIZE_TYPE uint32_tRTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)TIM_SR_CC1OF_Pos (9U)ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_MskWWDG_CR_WDGA WWDG_CR_WDGA_MskCAN_F5R1_FB12_Pos (12U)ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)bitplaneCAN_F11R2_FB9 CAN_F11R2_FB9_MskRCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_MskIS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)FSMC_PCR2_TCLR_Pos (9U)FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)CAN_TSR_LOW2 CAN_TSR_LOW2_MskTIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)MSN_STCRASH_MAIN_H RCC_APB1LPENR_UART5LPEN_Pos (20U)RCC_APB1LPENR_TIM6LPEN_Pos (4U)RTC_Alarm_IRQnDBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)CAN_RF1R_FULL1_Pos (3U)CAN_FA1R_FACT23_Pos (23U)CAN_F4R2_FB9_Pos (9U)SIG_ATOMIC_MAX __SIG_ATOMIC_MAX__SYSCFG_EXTICR3_EXTI10_PA 0x00000000UCAN_TSR_TERR0 CAN_TSR_TERR0_MskFSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)I2C_TRISE_TRISE_Pos (0U)ulTaskNotifyValueClear(xTask,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )__USER_LABEL_PREFIX__ RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_MskADC_CR2_ALIGN_Pos (11U)__SIZE_MAX__ 0xffffffffUETH_DMASR_RS ETH_DMASR_RS_Msk__LDBL_DENORM_MIN__ 4.9406564584124654e-324LTIM_CCR1_CCR1_Pos (0U)EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk_GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE(A) RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_MskCAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_MskCAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)CAN_F11R1_FB19 CAN_F11R1_FB19_MskUSB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_MskCAN_F11R2_FB4_Pos (4U)FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)USB_OTG_DIEPMSK_INEPNEM_Pos (6U)EXTI_IMR_MR8 EXTI_IMR_MR8_MskRCC_APB1LPENR_TIM13LPEN_Pos (7U)RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_MskCAN_F11R2_FB31 CAN_F11R2_FB31_MskETH_MMCCR_MCP_Pos (4U)I2C3 ((I2C_TypeDef *) I2C3_BASE)SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_MskCAN_F7R2_FB8_Pos (8U)CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)LL_GPIO_AF_8 (0x0000008U)CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )_WANT_IO_C99_FORMATS 1_REENT_CHECK_MISC(ptr) _GLIBCXX_HAVE_ATTRIBUTE_VISIBILITY 1EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)LL_DBGMCU_TRACE_NONE 0x00000000UUSB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_MskUSB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_MskSDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_MskETH_MMCRIR_RFCES_Pos (5U)CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)CAN_F1R2_FB26 CAN_F1R2_FB26_MskINT8_MINGPIO_MODER_MODE8 0x00030000UCAN_F7R1_FB16_Pos (16U)EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)CAN_FA1R_FACT CAN_FA1R_FACT_MskDCMI_CWSIZE_CAPCNT_Pos (0U)LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)RTC_ISR_WUTWF RTC_ISR_WUTWF_MskTIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)_GLIBCXX_FLOAT_IS_IEEE_BINARY32 1__SEV() __ASM volatile ("sev")LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0)FSMC_BCR1_ASYNCWAIT_Pos (15U)USB_OTG_GRSTCTL_DMAREQ_Pos (30U)RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_MskCAN_FM1R_FBM10 CAN_FM1R_FBM10_MskDCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_MskCAN_F10R1_FB14 CAN_F10R1_FB14_Msk__DEQUALIFY(type,var) ((type)(__uintptr_t)(const volatile void *)(var))CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_MskETH_DMAIER_TIE ETH_DMAIER_TIE_Msk__LDBL_MAX_EXP__ 1024ETH_MACFCR_PT_Pos (16U)RTC_TR_SU RTC_TR_SU_MskIPSR_ISR_Msk (0x1FFUL )CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)CAN_F13R2_FB20 CAN_F13R2_FB20_MskLL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000UFSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)RCC_CR_HSERDY_Pos (17U)CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_MskFSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_MskETH_MACA1HR_MBC_HBits7_0 0x10000000UFSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)__UINT_FAST16_MAX__ 0xffffffffUFLASH_CR_PSIZE FLASH_CR_PSIZE_MskUSB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)_GCC_MAX_ALIGN_T SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)CAN_F9R1_FB26_Pos (26U)BKP16RCAN_F3R2_FB12 CAN_F3R2_FB12_MskUSB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)CAN_F10R2_FB29 CAN_F10R2_FB29_MskSYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)__glibcxx_class_requires4(_a,_b,_c,_d,_e) SCB_BASE (SCS_BASE + 0x0D00UL)FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)RCC_CFGR_PPRE2_DIV1 0x00000000UTIM_SMCR_SMS TIM_SMCR_SMS_MskCAN_F10R2_FB21 CAN_F10R2_FB21_MskETH_PTPTSLR_STPNS_Pos (31U)ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)__cpp_init_captures 201803L__IM volatile constTIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)_GLIBCXX14_CONSTEXPR constexpr__malloc_like __attribute__((__malloc__))ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)LL_TIM_SR_CC4IF TIM_SR_CC4IFLL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN_GLIBCXX_LONG_DOUBLE_COMPATCAN_F7R1_FB15 CAN_F7R1_FB15_MskDCMI_CR_ENABLE DCMI_CR_ENABLE_MskUID_BASE_ADDRESS UID_BASERCC_AHB1ENR_GPIOHEN_Pos (7U)__cpp_if_constexpr 201606LETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)uxSemaphoreGetCount(xSemaphore) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )__FLT64_DENORM_MIN__ 4.9406564584124654e-324F64CAN_F10R2_FB28 CAN_F10R2_FB28_MskCAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_MskRCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)tskTaskControlBlock__locks_exclusive(...) __lock_annotate(exclusive_lock_function(__VA_ARGS__))RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_MskSYSCFG_EXTICR3_EXTI9_PE 0x00000040ULL_TIM_DMABURST_BASEADDR_CR1 0x00000000URCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)__ARM_FEATURE_IDIV 1GPIO_AFRL_AFSEL5_1 0x00200000ULL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7ENLL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN_WCHAR_T_DECLARED _GLIBCXX_HAVE_SLEEP 1FSMC_BTR2_DATLAT_Pos (24U)CAN_F8R2_FB12_Pos (12U)__CC_SUPPORTS_INLINE 1SYSCFG_EXTICR4_EXTI13_PB 0x00000010UUSB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)GPIO_AFRH_AFSEL13_1 0x00200000UADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_MskFSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)traceEVENT_GROUP_WAIT_BITS_END(xEventGroup,uxBitsToWaitFor,xTimeoutOccurred) ( void ) xTimeoutOccurred__lockable __lock_annotate(lockable)_GLIBCXX_HAVE_GETIPINFO 1LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)TIM_CCMR2_IC4PSC_Pos (10U)FSMC_PCR4_TAR FSMC_PCR4_TAR_MskCAN_F11R2_FB28_Pos (28U)FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)CAN_F9R2_FB2 CAN_F9R2_FB2_MskRCC_CSR_RMVF_Pos (24U)DMA_LISR_FEIF2 DMA_LISR_FEIF2_MskRCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)RCC_APB1LPENR_TIM2LPEN_Pos (0U)USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)_GLIBCXX_MAKE_MOVE_IF_NOEXCEPT_ITERATOR(_Iter) std::__make_move_if_noexcept_iterator(_Iter)ICERETH_DMAOMR_TTC_128Bytes 0x00004000UMSN_TSKMEM_H CAN_F12R2_FB10 CAN_F12R2_FB10_MskSDIO_MASK_DBCKENDIE_Pos (10U)_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0I2C_CR1_ALERT I2C_CR1_ALERT_MskSYSCFG_EXTICR3_EXTI9_PC 0x00000020USCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)__LLFRACT_FBIT__ 63USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)DMA_SxCR_MBURST DMA_SxCR_MBURST_MskFSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)ETH_MMCTGFSCCR_TGFSCC_Pos (0U)EXTI_FTSR_TR7 EXTI_FTSR_TR7_MskCAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_MskLIFCRETH_DMASR_RPS_Queuing_Pos (17U)TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)__NULLABILITY_PRAGMA_POP CAN_F2R1_FB12_Pos (12U)EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_MskCAN_F8R2_FB4 CAN_F8R2_FB4_MskFSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_MskCAN_F1R2_FB13 CAN_F1R2_FB13_MskFSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_MskEXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)CAN_F11R1_FB5_Pos (5U)GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)_TIMER_T_ unsigned longGPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)RCC_AHB1ENR_DMA2EN_Pos (22U)CAN_TSR_LOW2_Pos (31U)_NEWLIB_VERSION_H__ 1ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_MskCAN_F8R2_FB20 CAN_F8R2_FB20_MskFSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)CAN_F7R1_FB9_Pos (9U)RTC_ALRMBR_MNT RTC_ALRMBR_MNT_MskCAN_F2R2_FB25 CAN_F2R2_FB25_MskFSMC_SR4_IFEN FSMC_SR4_IFEN_MskCAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_MskUSB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)EXTI_EMR_EM7 EXTI_EMR_MR7RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)FSMC_SR4_ILS FSMC_SR4_ILS_MskFSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)listSET_LIST_ITEM_VALUE(pxListItem,xValue) ( ( pxListItem )->xItemValue = ( xValue ) )_GLIBCXX_END_NAMESPACE_CONTAINER FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)CAN_FM1R_FBM12_Pos (12U)FSMC_BWTR4_DATAST_7 (0x80UL << FSMC_BWTR4_DATAST_Pos)EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)SDIO_STA_CMDREND_Pos (6U)EXTI_PR_PR16_Pos (16U)ADC_CSR_AWD3_Pos (16U)DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)RCC_AHB2RSTR_OTGFSRST_Pos (7U)SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_MskRCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk__ARM_FEATURE_FP16_SCALAR_ARITHMETICxTaskNotifyGiveIndexed(xTaskToNotify,uxIndexToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_MskUSB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_MskETH_DMAIER_ERIE_Pos (14U)PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)LL_TIM_DIER_COMIE TIM_DIER_COMIECAN_MSR_SLAKI_Pos (4U)FLASH_CR_SER_Pos (1U)DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_MskSCB_ICSR_PENDSVSET_Pos 28UUSB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)CAN_FA1R_FACT6_Pos (6U)CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)CAN_F11R1_FB8 CAN_F11R1_FB8_MskEXTI_EMR_EM22 EXTI_EMR_MR22LCKRDMA_SxM1AR_M1A_Pos (0U)SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)RTC_ALRMAR_DU_Pos (24U)__catch(X) if (false)EXTI_EMR_MR5 EXTI_EMR_MR5_MskADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)CCMR2CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)CAN_FFA1R_FFA14_Pos (14U)USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_MskCAN_F4R2_FB11 CAN_F4R2_FB11_MsktraceBLOCKING_ON_STREAM_BUFFER_SEND(xStreamBuffer) __cpp_lib_type_trait_variable_templates 201510LCAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)CAN_F4R1_FB16_Pos (16U)ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_MskCAN_F0R1_FB3_Pos (3U)__unused __attribute__((__unused__))TIM_CCMR2_CC4S_Pos (8U)ETH_MACA2HR_MBC_LBits31_24 0x08000000UCAN_F13R1_FB21 CAN_F13R1_FB21_MskSYSCFG_EXTICR2_EXTI5_Pos (4U)TIM_DIER_CC3IE_Pos (3U)FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)DAC_CR_BOFF2 DAC_CR_BOFF2_MskDCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)CAN_FFA1R_FFA6_Pos (6U)USART_CR1_TE USART_CR1_TE_MskADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)SCB_SHCSR_BUSFAULTENA_Pos 17UCAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)I2C_SR2_PEC_Pos (8U)FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)__WCHAR_UNSIGNED__ 1CAN_F5R1_FB4 CAN_F5R1_FB4_MskRCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)__ARM_ARCH_EXT_IDIV__ 1GPIO_BSRR_BR_8 GPIO_BSRR_BR8USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)LL_FLASH_DisableInstCacheIWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)CAN_F7R2_FB2_Pos (2U)CAN_F3R1_FB2_Pos (2U)ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)RCC_APB1LPENR_WWDGLPEN_Pos (11U)ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)__is_aligned(x,y) __builtin_is_aligned(x, y)USB_OTG_HPRT_PENCHNG_Pos (3U)USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_MskCAN_F6R1_FB26_Pos (26U)TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_MskTIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_MskSYSCFG_EXTICR3_EXTI11_PG 0x00006000U__GCC_ATOMIC_LLONG_LOCK_FREE 1PWR_CR_PLS_LEV2 0x00000040USDIO_MASK_TXFIFOEIE_Pos (18U)__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKxQueueSendToBackFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1CAN_F4R1_FB6 CAN_F4R1_FB6_MskUSB_OTG_DIEPCTL_CNAK_Pos (26U)CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1CAN_F3R2_FB6 CAN_F3R2_FB6_MskTIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)traceSTREAM_BUFFER_DELETE(xStreamBuffer) EXTI_RTSR_TR8_Pos (8U)ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)DAC1 ((DAC_TypeDef *) DAC_BASE)SYSCFG_EXTICR3_EXTI11_PD 0x00003000URCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)ETH_MMCCR_MCFHP_Pos (5U)EXTI_SWIER_SWIER16_Pos (16U)IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))CAN_F9R2_FB29_Pos (29U)CAN_F5R2_FB12_Pos (12U)ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)CAN_F1R1_FB27 CAN_F1R1_FB27_MskRCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_MskRCC_APB1ENR_TIM5EN_Pos (3U)CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)__nosanitizethread CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)CAN_F2R2_FB8 CAN_F2R2_FB8_MskGPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)FSMC_BCR2_MBKEN_Pos (0U)CAN_F5R2_FB9_Pos (9U)RCC_AHB1RSTR_GPIOIRST_Pos (8U)I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_MskRTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_MskLL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOPCAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)GPIO_MODER_MODER5_Pos (10U)CAN_FS1R_FSC4 CAN_FS1R_FSC4_MskFSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)SIZE_MAXCAN_TI1R_STID CAN_TI1R_STID_MskI2C_OAR1_ADD8_9 0x00000300USYSCFG_EXTICR1_EXTI2_PI 0x00000800UGPIO_AFRL_AFSEL4_2 0x00040000UDMA_SxCR_PL DMA_SxCR_PL_MskI2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)SPI_CR2_RXNEIE_Pos (6U)I2C_SR1_OVR_Pos (11U)CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)GPIO_AFRH_AFSEL12_2 0x00040000UCAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCENGPIO_OTYPER_OT_13 GPIO_OTYPER_OT13CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)GPIO_MODER_MODE2 0x00000030UUSB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_MskCAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)CAN_F3R1_FB13 CAN_F3R1_FB13_MskUSB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)EXTI_IMR_MR13 EXTI_IMR_MR13_MskRCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_MskUSB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk__WCHAR_T DT_RANGE_4 ((uint8_t)0xE0)CoreDebug_DEMCR_MON_REQ_Pos 19UTIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_MskUSB_OTG_DSTS_EERR_Pos (3U)CAN_F7R1_FB21 CAN_F7R1_FB21_Msk__CC_SUPPORTS___FUNC__ 1WWDG_CR_T3 WWDG_CR_T_3INCLUDE_xTaskGetIdleTaskHandle 0FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk__cpp_aligned_new 201606LCAN_F7R2_FB16_Pos (16U)I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_MskRCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_MskRTC_TAFCR_TAMP1INSEL_Pos (16U)CAN_F11R1_FB17_Pos (17U)SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_MskxTaskHandle TaskHandle_tlistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE OSPEEDRUSB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)USB_OTG_DCTL_SGINAK_Pos (7U)USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_MskFSMC_BTR2_ACCMOD_Pos (28U)USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)DMA2_Stream3_IRQnCAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM12))MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)EXTI_FTSR_TR19 EXTI_FTSR_TR19_MskCAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8) || ((INSTANCE) == TIM9) || ((INSTANCE) == TIM10) || ((INSTANCE) == TIM11) || ((INSTANCE) == TIM12) || ((INSTANCE) == TIM13) || ((INSTANCE) == TIM14))SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)_WINT_T USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_MskRTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)ETH_DMAOMR_FEF_Pos (7U)USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)TIM_DIER_CC4IE TIM_DIER_CC4IE_MskWWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)advanceSDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)__DBL_NORM_MAX__ double(1.7976931348623157e+308L)CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)CAN_F9R2_FB26_Pos (26U)FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)CAN_F12R2_FB28 CAN_F12R2_FB28_MskLL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)INTMAX_C(c) __INTMAX_C(c)CAN_F13R1_FB27_Pos (27U)CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)RTC_DR_YT RTC_DR_YT_MskUSB_OTG_GRXSTSP_DPID_Pos (15U)ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_MskADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_MskUSB_OTG_HCINTMSK_NYET_Pos (6U)LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2_GLIBCXX_NOEXCEPT_QUAL noexcept (_NE)GPIO_ODR_OD1 0x00000002UCAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)CAN_TSR_ALST1 CAN_TSR_ALST1_MskDAC_SWTRIGR_SWTRIG2_Pos (1U)USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_MskUSB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)GPIO_ODR_ODR_10 GPIO_ODR_OD10FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)CoreDebug_DEMCR_MON_STEP_Pos 18URCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)CAN_RDL0R_DATA3_Pos (24U)SYSCFG_EXTICR2_EXTI6_PD 0x00000300UGPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0RTC_ALRMAR_MSK4_Pos (31U)CAN_F5R2_FB0_Pos (0U)SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_MskRTC_ALRMBR_HU_Pos (16U)RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk_ATTRIBUTE(attrs) __attribute__ (attrs)CAN_F8R1_FB4 CAN_F8R1_FB4_MskEXTI_PR_PR16 EXTI_PR_PR16_MskETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)ETH_DMASR_TPS_Reading_Pos (20U)__glibcxx_function_requires(...) CAN_F8R1_FB21 CAN_F8R1_FB21_MskFSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_MskETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)__USA_FBIT__ 16ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)I2C_SR1_OVR I2C_SR1_OVR_MskDMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)CAN_F0R2_FB1 CAN_F0R2_FB1_MskITM_IMCR_INTEGRATION_Pos 0UCAN_F12R2_FB13_Pos (13U)TIM_SR_COMIF_Pos (5U)xTaskNotifyIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_MskADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)FLASH_OPTCR_nWRP_11 (0x800UL << FLASH_OPTCR_nWRP_Pos)WWDG_CR_T0 WWDG_CR_T_0GPIO_AFRH_AFSEL12_0 0x00010000UETH_MMCCR_ROR_Pos (2U)UINT_LEAST64_MAX_GLIBCXX_HAVE_TRUNCATE 1SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)GPIO_ODR_OD13 0x00002000UCAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)__weak_symbol __attribute__((__weak__))USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)__requires_shared(...) __lock_annotate(shared_locks_required(__VA_ARGS__))__glibcxx_class_requires3(_a,_b,_c,_d) CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)DMA_SxCR_ACK DMA_SxCR_ACK_MskCAN_F1R1_FB27_Pos (27U)__STM32F2xx_LL_SYSTEM_H LL_DMA_SetDataTransferDirectionGPIO_ODR_OD14 0x00004000UFSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)CAN_F0R1_FB3 CAN_F0R1_FB3_MskCAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)__SIZEOF_WINT_T__ 4I2C_OAR1_ADD1_7 0x000000FEU_ZN5crash6MatrixC2EvRCC_CFGR_MCO2 RCC_CFGR_MCO2_MskSCB_CPUID_ARCHITECTURE_Pos 16U__LFRACT_EPSILON__ 0x1P-31LRUSB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_MskGPIO_MODER_MODE6_1 0x00002000UFSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_MskRCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)__ULLFRACT_FBIT__ 64CAN_F4R1_FB12 CAN_F4R1_FB12_MskCAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)TIM_BDTR_BKP_Pos (13U)TPI_SPPR_TXMODE_Msk (0x3UL )CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRUSB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)ADC_JSQR_JL ADC_JSQR_JL_MskUSB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_MskLL_TIM_UPDATESOURCE_REGULAR 0x00000000UCAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)RTC_ALRMBR_MSK1_Pos (7U)CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)RCC_APB1ENR_UART4EN_Pos (19U)ETH_MACFFR_PCF_BlockAll_Pos (6U)TIM_CCER_CC4NP_Pos (15U)SDIO_POWER_PWRCTRL_Pos (0U)__WINT_MAX__ 0xffffffffUADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)SCB_CCR_BFHFNMIGN_Pos 8UETH_MACCR_IFG_40Bit 0x000E0000UTIM_CR2_OIS2_Pos (10U)GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)RTC_CR_TSIE_Pos (15U)USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)CAN_F0R2_FB13_Pos (13U)FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_MskTIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)GPIO_PUPDR_PUPD7_1 0x00008000UDBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_MskGPIO_IDR_IDR_9 GPIO_IDR_ID9CAN_F3R2_FB31 CAN_F3R2_FB31_MskRCC_AHB1LPENR_DMA1LPEN_Pos (21U)ESP_USART_IRQ_HANDLER USART6_IRQHandlerRCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_MskCAN_F10R2_FB13 CAN_F10R2_FB13_MskFSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10CAN_TSR_TME_Pos (26U)FSMC_PCR3_PWID FSMC_PCR3_PWID_MskRCC_CR_HSIRDY_Pos (1U)RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)__ATOMIC_ACQUIRE 2__FLT_MIN_10_EXP__ (-37)CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_MskRTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)traceQUEUE_SEND_FROM_ISR(pxQueue) RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)CAN_IER_FMPIE1_Pos (4U)FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)__trylocks_shared(...) __lock_annotate(shared_trylock_function(__VA_ARGS__))__Long longDBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)USB_OTG_NPTXFSA USB_OTG_NPTXFSA_MskLL_TIM_CHANNEL_CH4 TIM_CCER_CC4ESDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_MskDMA1_Stream3_IRQnFSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_MskCAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)CAN_F2R2_FB23_Pos (23U)FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)ADC_CR1_OVRIE ADC_CR1_OVRIE_MskCAN_F1R1_FB3_Pos (3U)CAN_FS1R_FSC21 CAN_FS1R_FSC21_MskRCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_MskLL_MPU_REGION_NUMBER6 0x06UCAN_FA1R_FACT12_Pos (12U)CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)ADC_CR1_AWDCH ADC_CR1_AWDCH_MskETH_MACFCR_TFCE_Pos (1U)CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)TypeChangeTempMultiCAN_F12R1_FB29 CAN_F12R1_FB29_MskCAN_IER_EWGIE CAN_IER_EWGIE_MskUSB_OTG_GUSBCFG_HNPCAP_Pos (9U)RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_MskSDIO_STA_CEATAEND SDIO_STA_CEATAEND_MskCAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)DAC_CR_EN1 DAC_CR_EN1_MskRCC_APB1ENR_TIM2EN_Pos (0U)CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)ETH_MACPMTCSR_WFFRPR_Pos (31U)__CHAR_BIT__ 8CAN_F7R1_FB11_Pos (11U)__I volatileSPI_I2SCFGR_CHLEN_Pos (0U)portSETUP_TCB(pxTCB) ( void ) pxTCB__glibcxx_requires_non_empty_range(_First,_Last) SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_MskETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)ETH_DMAIER_RWTIE_Pos (9U)DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)CAN_F10R1_FB27_Pos (27U)FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)traceQUEUE_RECEIVE_FROM_ISR_FAILED(pxQueue) PWR_CR_PLS PWR_CR_PLS_MskDCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)UINT_FAST32_MAX __UINT_FAST32_MAX__ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)INT_FAST32_MAX __INT_FAST32_MAX__MAX_BHEAP_BLOCK_SIZE ((1 << 14) - 1)ADC_CR1_AWDCH_Pos (0U)CAN_F8R2_FB13 CAN_F8R2_FB13_Msk__requires_unlocked(...) __lock_annotate(locks_excluded(__VA_ARGS__))_PSTL_PRAGMA_SIMD _PSTL_PRAGMA(omp simd)BKPSRAM_BASE 0x40024000ULCAN_F2R2_FB18 CAN_F2R2_FB18_MskDMA1_Stream0_BASE (DMA1_BASE + 0x010UL)USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)FSMC_SR3_ILEN_Pos (4U)__PTRDIFF_T UINTMAX_CCAN_F11R1_FB24 CAN_F11R1_FB24_MskUSART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)RCC_BDCR_LSEON_Pos (0U)__FLT_EVAL_METHOD_TS_18661_3__ 0CAN_F4R2_FB27_Pos (27U)CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_MskCAN_F8R1_FB0_Pos (0U)CAN_F9R1_FB21_Pos (21U)FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_MskTIM_SR_CC1OF TIM_SR_CC1OF_MskFSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)CAN_F5R1_FB5 CAN_F5R1_FB5_MskETH_MACDBGR_MTP ETH_MACDBGR_MTP_MskETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)xSemaphoreGetMutexHolderFromISR(xSemaphore) xQueueGetMutexHolderFromISR( ( xSemaphore ) )ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)TIM_SMCR_ECE TIM_SMCR_ECE_MskCAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSENpdFREERTOS_ERRNO_ENOPROTOOPT 109TIM_SR_CC2OF_Pos (10U)ETH_MACSR_TSTS_Pos (9U)__min_size(x) (x)SYSCFG_EXTICR3_EXTI10_PC 0x00000200UUSB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_MskUSB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR__ARM_FEATURE_FP16_FMLSDIO_MASK_RXFIFOHFIE_Pos (15U)FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)listSET_LIST_ITEM_OWNER(pxListItem,pxOwner) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )CAN_F9R1_FB15_Pos (15U)FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)CAN_F5R1_FB13_Pos (13U)SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)__FLT64_MAX__ 1.7976931348623157e+308F64RCC_AHB1ENR_CRCEN_Pos (12U)CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)__EXPRCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_MskDBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_MskUINTPTR_MAXCAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)LL_TIM_DIER_BIE TIM_DIER_BIEUSB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)CAN_F13R1_FB13 CAN_F13R1_FB13_MskRCC_CFGR_PPRE2_DIV2 0x00008000ULL_TIM_SR_CC1OF TIM_SR_CC1OFETH_DMABMR_SR_Pos (0U)I2C3_EV_IRQnCAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)DMA_HIFCR_CTEIF5_Pos (9U)USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)SPI_I2SPR_ODD SPI_I2SPR_ODD_MskUSB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)RTC_BKP17R RTC_BKP17R_MskARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)UINT16_MAX __UINT16_MAX___GLIBCXX_STDIO_EOF -1__FLT_EPSILON__ 1.1920928955078125e-7FETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_MskFSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)SDIO_STA_RXFIFOHF_Pos (15U)__LONG_WIDTH__ 32RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)DCMI_CR_JPEG_Pos (3U)ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_MskNVIC_H GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3FLASH_OPTCR_nWRP_6 (0x040UL << FLASH_OPTCR_nWRP_Pos)FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)titleINTMAX_MINRTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)CAN_F7R2_FB26 CAN_F7R2_FB26_MskSYSCFG_EXTICR3_EXTI8_PA 0x00000000UADC_SR_OVR ADC_SR_OVR_Msk__ULLFRACT_IBIT__ 0USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)EXTI_RTSR_TR19 EXTI_RTSR_TR19_MskWWDG_CFR_WDGTB_Pos (7U)DCMI_IER_ERR_IE DCMI_IER_ERR_IE_MskUSB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)GPIO_OSPEEDR_OSPEED14 0x30000000UFLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)CAN_F10R2_FB1 CAN_F10R2_FB1_MskGPIO_OSPEEDR_OSPEED9_1 0x00080000ULL_TIM_IC_POLARITY_RISING 0x00000000UCAN_F7R2_FB18_Pos (18U)CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_MskMPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)EXTI_IMR_MR11_Pos (11U)CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_MskADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)CAN_RI0R_STID CAN_RI0R_STID_MskDMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)TIM_OR_TI1_RMP TIM_OR_TI1_RMP_MskSYSCFG_EXTICR1_EXTI3_PD 0x00003000URTC_ALRMAR_DT_Pos (28U)CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)GPIO_PUPDR_PUPD12 0x03000000URCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk_GLIBCXX_HAVE_STDLIB_H 1CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)CAN_F3R2_FB1_Pos (1U)LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WSFSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)I2C_SR1_AF_Pos (10U)CAN_F13R2_FB27_Pos (27U)USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)CAN_FA1R_FACT0 CAN_FA1R_FACT0_MskFSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)CAN_F0R1_FB10 CAN_F0R1_FB10_MskCAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)CAN_F9R2_FB12 CAN_F9R2_FB12_MskPWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)CAN_F3R2_FB17 CAN_F3R2_FB17_MskI2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)__NEWLIB_MINOR__ 4USB_OTG_GINTMSK_ISOODRPM_Pos (14U)LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PLEXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)ADC_CCR_ADCPRE ADC_CCR_ADCPRE_MskRCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)EXTI_RTSR_TR13_Pos (13U)CAN_F6R2_FB0_Pos (0U)WWDG ((WWDG_TypeDef *) WWDG_BASE)FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)ETH_MACSR_MMCS ETH_MACSR_MMCS_MskEXTI_IMR_MR5 EXTI_IMR_MR5_MskADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)__ARM_FEATURE_MVE_REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last)FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_MskRCC_AHB1LPENR_SRAM1LPEN_Pos (16U)CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk_GLIBCXX_HAVE_STDALIGN_H 1errQUEUE_YIELD ( -5 )ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk_GLIBCXX_HAS_NESTED_TYPE(_NTYPE) template> struct __has_ ##_NTYPE : false_type { }; template struct __has_ ##_NTYPE<_Tp, __void_t> : true_type { };CAN_FA1R_FACT8_Pos (8U)FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2FLASH_OPTCR_RDP_Pos (8U)CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk__DECONST(type,var) ((type)(__uintptr_t)(const void *)(var))CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)ETH_DMASR_TS_Pos (0U)LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000UADC_CR2_SWSTART_Pos (30U)ETH_DMASR_TPS_Stopped 0x00000000UGPIO_AFRL_AFSEL6_2 0x04000000URCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_MskRCC_AHB2ENR_DCMIEN_Pos (0U)RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_MskADC_SMPR2_SMP9_Pos (27U)traceEVENT_GROUP_SET_BITS(xEventGroup,uxBitsToSet) configTIMER_QUEUE_LENGTH 10CAN_F9R1_FB4 CAN_F9R1_FB4_MskDMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_MskCAN_BTR_BRP_Pos (0U)CAN_F1R2_FB27_Pos (27U)EXTI_PR_PR22_Pos (22U)SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_MskRTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)RTC_ISR_INITF_Pos (6U)__GNUC_WIDE_EXECUTION_CHARSET_NAME "UTF-32LE"TIM_SMCR_TS_Pos (4U)SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)GPIO_BSRR_BR12 0x10000000ULL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2ENUSB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk__SA_FBIT__ 15FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)DAC_CR_TEN1 DAC_CR_TEN1_MskCAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)CAN_F11R2_FB19_Pos (19U)SYSCFG_EXTICR1_EXTI1_Pos (4U)IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)DCMI_IER_VSYNC_IE_Pos (3U)DAC_SR_DMAUDR2_Pos (29U)ADC_SQR2_SQ10 ADC_SQR2_SQ10_MskRTC_BKP11R_Pos (0U)CAN_F2R1_FB6 CAN_F2R1_FB6_MskxSemaphoreCreateRecursiveMutexStatic(pxStaticSemaphore) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)RCC_CFGR_HPRE_DIV16 0x000000B0UCAN_F10R1_FB22_Pos (22U)ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_MskCAN_F8R1_FB6 CAN_F8R1_FB6_MskCAN1_TX_IRQnEXTI_EMR_MR16 EXTI_EMR_MR16_MskUSB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)18DMA_Stream_TypeDefCAN_F7R2_FB6 CAN_F7R2_FB6_MskCAN_F6R1_FB18_Pos (18U)CAN_F6R1_FB15_Pos (15U)GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_MskADC_CR1_AWDSGL ADC_CR1_AWDSGL_MskGPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)ETH_DMABMR_RDP_4Beat 0x00080000URCC_CFGR_HPRE_DIV64 0x000000C0UDMA_LISR_FEIF1_Pos (6U)SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)CAN_F6R2_FB23_Pos (23U)__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1RTC_ALRMAR_DU RTC_ALRMAR_DU_MskEXTI_IMR_MR4_Pos (4U)FSMC_BCR3_WREN_Pos (12U)USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)SYSCFG_EXTICR3_EXTI9_PA 0x00000000UEXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)RCC_APB1ENR_CAN2EN_Pos (26U)SysTick_CTRL_COUNTFLAG_Pos 16UTIM_CCER_CC3NE_Pos (10U)FSMC_SR2_IFS_Pos (2U)RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)CoreDebug_DHCSR_C_SNAPSTALL_Pos 5UFSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_MskCAN_FS1R_FSC26_Pos (26U)mtCOVERAGE_TEST_MARKER() RCC_APB2ENR_TIM10EN_Pos (17U)RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)APSR_V_Msk (1UL << APSR_V_Pos)__cpp_noexcept_function_type 201510LCAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)__FLOAT_TYPE floatSDIO_STA_CCRCFAIL_Pos (0U)FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)FSMC_SR2_FEMPT FSMC_SR2_FEMPT_MskCAN_F6R2_FB8 CAN_F6R2_FB8_MskDBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)TypeGetCalibrationFLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_MskETH_MACFCR_UPFD ETH_MACFCR_UPFD_MskGPIO_BSRR_BR14 0x40000000URCC_APB2RSTR_TIM9RST_Pos (16U)SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)CAN_F8R1_FB14 CAN_F8R1_FB14_MskRCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)CAN_TSR_TME1_Pos (27U)RCC_CFGR_PPRE2_Pos (13U)CAN_F2R1_FB19 CAN_F2R1_FB19_MskportTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR(x) ( void ) xCAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)USB_OTG_HCINTMSK_TXERRM_Pos (7U)_scidataADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)FSMC_BTR1_BUSTURN_Pos (16U)GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)__cpp_lib_tuple_element_t 201402LETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)traceINCREASE_TICK_COUNT(x) CAN_FS1R_FSC18_Pos (18U)ADC_DR_ADC2DATA_Pos (16U)SPI_CR1_SPE SPI_CR1_SPE_MskCAN_FS1R_FSC6 CAN_FS1R_FSC6_MskADC_SQR1_SQ15_Pos (10U)__GCC_CONSTRUCTIVE_SIZE 64EXTI_SWIER_SWIER15_Pos (15U)TIM_CCER_CC2NE TIM_CCER_CC2NE_MskMMFARADC_SMPR1_SMP12 ADC_SMPR1_SMP12_MskCoreDebug_DEMCR_MON_PEND_Pos 17USCnSCB_ACTLR_DISMCYCINT_Msk (1UL )FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)WWDG_CR_T6 WWDG_CR_T_6TypeNoneCAN_F13R2_FB8_Pos (8U)FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_MskCoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)DCMI_MIS_ERR_MIS_Pos (2U)USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk__glibcxx_requires_string_len(_String,_Len) _GLIBCXX_HAVE_LIMIT_VMEM 0SDIO_STA_STBITERR_Pos (9U)FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_MskSDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_MskCAN_F6R1_FB1_Pos (1U)PWR_CR_PLS_LEV7 0x000000E0UCAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)CounterModeUSART_CR1_TXEIE USART_CR1_TXEIE_MskFSMC_BCR4_WRAPMOD_Pos (10U)SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_MskCAN_RF1R_FMP1 CAN_RF1R_FMP1_MskDMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)USB_OTG_EP_REG_SIZE 0x20ULADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)__UINT_FAST64_MAX__ 0xffffffffffffffffULLTIM11_BASE (APB2PERIPH_BASE + 0x4800UL)RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_MskFSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_MskRTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)TIM_CCER_CC2NE_Pos (6U)PWR_CSR_SBF_Pos (1U)ETH_MMCRIMR_RFAEM_Pos (6U)GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)__cpp_lib_as_const 201510L_PSTL_CPP14_MAKE_REVERSE_ITERATOR_PRESENT (_MSC_VER >= 1900 || __cplusplus >= 201402L || __cpp_lib_make_reverse_iterator == 201402)__cpp_lib_launder 201606L__LFRACT_MIN__ (-0.5LR-0.5LR)CAN_F3R2_FB24 CAN_F3R2_FB24_MskRCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)LL_GPIO_AF_0 (0x0000000U)SCB_ICSR_PENDSVCLR_Pos 27UGPIO_AFRL_AFSEL6_0 0x01000000UCAN_F13R1_FB22_Pos (22U)CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFURCC_APB1RSTR_SPI3RST_Pos (15U)FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_MskGPIO_AFRH_AFSEL14_0 0x01000000ULL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS__UINTMAX_MAX__ 0xffffffffffffffffULLRCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)_GLIBCXX_STDIO_SEEK_END 2RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_MskCAN_FM1R_FBM2 CAN_FM1R_FBM2_MskCAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk__cpp_fold_expressions 201603LGPIO_OTYPER_OT_9 GPIO_OTYPER_OT9CAN_F7R1_FB27 CAN_F7R1_FB27_MskCAN_MSR_INAK CAN_MSR_INAK_Mskdelay_msCAN_F5R2_FB3_Pos (3U)USART_CR3_NACK USART_CR3_NACK_MskUSB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)CAN_F7R2_FB22_Pos (22U)ADC_CCR_DMA ADC_CCR_DMA_MskI2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)CAN_F13R1_FB16_Pos (16U)CAN_F8R2_FB8_Pos (8U)AdcCalibrationResultLL_DMA_OFFSETSIZE_PSIZE 0x00000000UGPIO_MODER_MODER13_Pos (26U)CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)TIM_EGR_CC4G TIM_EGR_CC4G_Msk__ARM_FEATURE_SHA2__BEGIN_DECLS extern "C" {EXTI_SWIER_SWIER2_Pos (2U)USB_OTG_DOEPMSK_NAKM_Pos (13U)CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)LL_TIM_OCSTATE_DISABLE 0x00000000UFSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)CAN_FS1R_FSC13 CAN_FS1R_FSC13_MskCAN_FS1R_FSC9 CAN_FS1R_FSC9_MskFSMC_PMEM3_MEMSET3_Pos (0U)__DEVOLATILE(type,var) ((type)(__uintptr_t)(volatile void *)(var))ESP_HEAP_SIZE (15*1024)CAN_F5R1_FB1 CAN_F5R1_FB1_MskFSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_MskLL_TIM_SR_TIF TIM_SR_TIFUSB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk__swappable_with_detailsCAN_F4R2_FB1 CAN_F4R2_FB1_MskUSB_OTG_GOTGINT_SEDET_Pos (2U)CAN_TI2R_STID_Pos (21U)RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_MskDMA_SxCR_MSIZE DMA_SxCR_MSIZE_MskportEND_SWITCHING_ISR(xSwitchRequired) if( xSwitchRequired != pdFALSE ) portYIELD()ETH_MACA2HR_SA ETH_MACA2HR_SA_MskRCC_AHB1LPENR_GPIOCLPEN_Pos (2U)SUCCESSUSB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_MskpdFREERTOS_BIG_ENDIAN 1USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_MskSPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_MskSDIO_CMD_NIEN_Pos (13U)CAN_F9R1_FB13 CAN_F9R1_FB13_Msk__UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_MskCAN_F1R1_FB22_Pos (22U)__glibcxx_requires_irreflexive_pred(_First,_Last,_Pred) EXTI_IMR_MR0_Pos (0U)GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RISEXTI_IMR_MR18 EXTI_IMR_MR18_MskSDIO_DCTRL_SDIOEN_Pos (11U)_RAND48_SEED_2 (0x1234)USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_MskFSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_MskFSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_MskconfigMINIMAL_STACK_SIZE ((uint16_t)128)FSMC_BCR2_MUXEN_Pos (1U)_GLIBCXX_HAVE_S_ISREG 1UINT64_CUINT_FAST16_MAXTIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)__FLT32_EPSILON__ 1.1920928955078125e-7F32portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()CAN_F1R2_FB2_Pos (2U)CAN_F3R2_FB3 CAN_F3R2_FB3_MskMSN_RAMFUNC_H USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)GPIO_PUPDR_PUPD13_0 0x04000000ULL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)WWDG_CFR_W5 WWDG_CFR_W_5DAC_CR_TSEL2 DAC_CR_TSEL2_MskUSB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)TPI_DEVID_NrTraceInput_Pos 0UCAN_F8R1_FB9 CAN_F8R1_FB9_MskRCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)traceQUEUE_PEEK_FAILED(pxQueue) ETH_MACDBGR_RFFL_Pos (8U)CAN_F1R1_FB16_Pos (16U)CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk_GLIBCXX_HAVE_LINK 1CAN_F4R2_FB8_Pos (8U)SYSCFG_EXTICR1_EXTI0_PB 0x00000001UCAN_F11R1_FB16 CAN_F11R1_FB16_MskUSB_OTG_DIEPCTL_MPSIZ_Pos (0U)USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_MskCoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCKLL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)CAN_F2R1_FB4 CAN_F2R1_FB4_MskCAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)ETH_MACCR_IFG_80Bit 0x00040000UCAN_F4R2_FB1_Pos (1U)WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)I2C_CR1_SMBUS_Pos (1U)USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)__FLT32_DIG__ 6CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)ADC_CSR_JEOC3_Pos (18U)TPI_FIFO0_ETM0_Pos 0USDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_MskGPIO_AFRL_AFSEL1_2 0x00000040UCAN_F13R1_FB0 CAN_F13R1_FB0_MskCAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)FSMC_PCR3_PTYP_Pos (3U)USART_CR1_PEIE_Pos (8U)operator boolADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_MskRCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk__cpp_impl_coroutine 201902LRCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0configTASK_NOTIFICATION_ARRAY_ENTRIES 1CAN_F3R1_FB26_Pos (26U)GPIO_PUPDR_PUPD8_0 0x00010000USDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)USB_OTG_DOEPMSK_NYETM_Pos (14U)GPIO_BSRR_BR_3 GPIO_BSRR_BR3CAN_F11R2_FB23 CAN_F11R2_FB23_Msk__ARM_FEATURE_FMAADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)__LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)__FLT64_MANT_DIG__ 53CAN_F4R2_FB23 CAN_F4R2_FB23_MskCRC_IDR_IDR_Pos (0U)RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk__datatype_type_tag(kind,type) CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)TPI_FIFO1_ITM2_Pos 16UCAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)GPIO_LCKR_LCK8_Pos (8U)ADC_CSR_DOVR2 ADC_CSR_OVR2RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)_ZN3srv8Servicer11PendRequest11TimeRequestD4EvGPIO_BSRR_BR_7 GPIO_BSRR_BR7TPI_FIFO0_ETM1_Pos 8UCAN_F11R2_FB18 CAN_F11R2_FB18_MskTIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)DWT_CTRL_POSTINIT_Pos 5UCAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)FSMC_ECCR2_ECC2_Pos (0U)ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)ETH_MACIMR_TSTIM_Pos (9U)RTC_BKP8R RTC_BKP8R_MskFSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)CAN_F2R2_FB12_Pos (12U)DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk_GLIBCXX_HAVE_UNISTD_H 1USB_OTG_GINTMSK_EOPFM_Pos (15U)DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_MskGPIO_OSPEEDR_OSPEED1_0 0x00000004UCAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)RCC_CIR_HSERDYC_Pos (19U)PTRDIFF_MAXFLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_MskCAN_F12R1_FB5_Pos (5U)queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U )NVIC_SRV_RXE_ACTV LL_DMA_IsActiveFlag_TE1SCB_AIRCR_VECTKEY_Pos 16U__cpp_lib_unwrap_ref 201811LCAN_F7R2_FB19 CAN_F7R2_FB19_MsktraceSTREAM_BUFFER_SEND_FROM_ISR(xStreamBuffer,xBytesSent) ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)__GNUC_MINOR__ 3FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)CAN_F0R2_FB14 CAN_F0R2_FB14_MskCAN_F8R1_FB9_Pos (9U)ETH_DMAIER_RIE_Pos (6U)CAN_F13R2_FB12 CAN_F13R2_FB12_MsklistGET_LIST_ITEM_VALUE(pxListItem) ( ( pxListItem )->xItemValue )TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)SYSCFG_EXTICR3_EXTI8_PG 0x00000006UCAN_FFA1R_FFA6 CAN_FFA1R_FFA6_MskETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)EXTI_EMR_MR15_Pos (15U)SYSCFG_EXTICR2_EXTI6_PH 0x00000700UINT32_MIN (-INT32_MAX - 1)USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_MskUSB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)SHCSRUSB_OTG_HOST_PORT_BASE 0x440ULADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)GPIO_PUPDR_PUPD5_0 0x00000400UCAN_F4R2_FB22_Pos (22U)CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)__SIZEOF_LONG__ 4ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)CoreDebug_DEMCR_VC_CORERESET_Pos 0UGPIO_AFRH_AFSEL9 0x000000F0UIS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM8))__FLT32_MAX_10_EXP__ 38CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_MskUSB_OTG_GINTMSK_USBSUSPM_Pos (11U)CAN_TDH0R_DATA4_Pos (0U)ETH_MACCR_BL_1 0x00000060UCAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)tskIDLE_PRIORITY ( ( UBaseType_t ) 0U )GPIO_OSPEEDR_OSPEED6_0 0x00001000USPI3 ((SPI_TypeDef *) SPI3_BASE)CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)CAN_FM1R_FBM5_Pos (5U)DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)ADC_CDR_DATA2_Pos (16U)USB_OTG_PCGCCTL_STOPCLK_Pos (0U)CAN_F4R2_FB16_Pos (16U)CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)CAN_TDH1R_DATA6_Pos (16U)IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2) || ((INSTANCE) == ADC3))_GLIBCXX_HAVE_MACHINE_ENDIAN_H 1__FLT32_HAS_DENORM__ 1CAN_F9R1_FB10_Pos (10U)GPIO_LCKR_LCK15_Pos (15U)TIM_CR1_ARPE TIM_CR1_ARPE_MskGPIO_MODER_MODE13_0 0x04000000UFSMC_BCR2_MWID_Pos (4U)configPRINTF(X) ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)SPI_CR2_FRF SPI_CR2_FRF_MskCAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)USB_OTG_GRXSTSP_PKTSTS_Pos (17U)USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_MskLL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)CAN_TDT2R_DLC_Pos (0U)CAN_ESR_EWGF_Pos (0U)GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1INT_LEAST8_MINCAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)SYSCFG_MEMRMP_MEM_MODE_Pos (0U)SysTick_CALIB_NOREF_Pos 31UDAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_MskSDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)DT_DELAY_3 ((uint8_t)0x1F)CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_MskSDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_MskTIM7 ((TIM_TypeDef *) TIM7_BASE)CAN_F9R1_FB20 CAN_F9R1_FB20_MskETH_PTPTSCR_TSITE_Pos (4U)CAN_F3R1_FB25 CAN_F3R1_FB25_MskRTC_ISR_RSF_Pos (5U)CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)CAN_F6R2_FB26_Pos (26U)CRC_CR_RESET_Pos (0U)USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_MskDMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_MskDMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)CAN_F7R2_FB21 CAN_F7R2_FB21_MskxTaskParameters TaskParameters_t___int_least8_t_defined 1ETH_DMABMR_PBL_32Beat 0x00002000UADC_SMPR2_SMP6 ADC_SMPR2_SMP6_MskDMA_HISR_HTIF6_Pos (20U)RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk__LL_TIM_CALC_ARR(__TIMCLK__,__PSC__,__FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)FSMC_BCR2_WRAPMOD_Pos (10U)RCC_CFGR_HPRE_DIV2 0x00000080UETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)SDIO_STA_TXFIFOHE_Pos (14U)__UFRACT_IBIT__ 0DWT_MASK_MASK_Msk (0x1FUL )__cmp_algUSB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)CAN_FS1R_FSC2_Pos (2U)CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)xQueueHandle QueueHandle_tDBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)__size_tDCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)ARM_MPU_ACCESS_NORMAL(OuterCp,InnerCp,IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)TPI_ITATBCTR0_ATREADY1_Msk (0x1UL )ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_MskSYSCFG_EXTICR2_EXTI5_PE 0x00000040U_SIZE_T_DEFINED ETH_MACCR_DC ETH_MACCR_DC_MskCAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)CAN_F5R1_FB11 CAN_F5R1_FB11_MskUSB_OTG_EPNUM USB_OTG_EPNUM_MskGPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12CAN_F0R1_FB26_Pos (26U)LL_DMA_DisableIT_HTFSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)__ARM_FEATURE_CRYPTOCAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)CAN_F10R2_FB5_Pos (5U)LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_MskSDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)CAN_RI1R_IDE CAN_RI1R_IDE_MskCAN_F7R1_FB22 CAN_F7R1_FB22_MskFLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_MskCAN_F6R2_FB9_Pos (9U)USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_MskUSB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIRCAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)TIM_DIER_UIE_Pos (0U)CAN_F2R1_FB2 CAN_F2R1_FB2_MskGPIO_ODR_OD10 0x00000400UUSART_CR1_OVER8 USART_CR1_OVER8_MskFSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)uint8_t_PSTL_VERSION_PATCH (_PSTL_VERSION % 10)CAN_F4R2_FB30 CAN_F4R2_FB30_MskTIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)CAN_F13R2_FB4_Pos (4U)CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)xQueueOverwriteFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)RCC_APB1ENR_I2C3EN_Pos (23U)CAN_F11R2_FB23_Pos (23U)char16_tETH_PTPTSCR_TSFCU_Pos (1U)CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)queueSEND_TO_BACK ( ( BaseType_t ) 0 )FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)__ULLACCUM_EPSILON__ 0x1P-32ULLKUSB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_MskUSB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_MskRTC_ALRMBR_SU_Pos (0U)FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)TIM_CCMR1_CC1S TIM_CCMR1_CC1S_MskETH_DMASR_FBES_Pos (13U)LL_TIM_CHANNEL_CH3 TIM_CCER_CC3EFSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_MskRTC_TR_HT RTC_TR_HT_MskRTC_TSTR_HT RTC_TSTR_HT_Msk__SIG_ATOMIC_WIDTH__ 32_GLIBCXX_TYPE_TRAITS 1USB_OTG_HCTSIZ_DOPING_Pos (31U)USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)DCMI_IRQnGPIO_PUPDR_PUPD1_1 0x00000008U__cpp_lib_result_of_sfinae 201210L__cpp_lib_to_address 201711LGPIO_MODER_MODER3 GPIO_MODER_MODER3_MskRCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_MskRTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)CAN_IER_EWGIE_Pos (8U)RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)LL_DMA_EnableIT_TETIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)pdFREERTOS_ERRNO_EINTR 4EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)__cpp_lib_integer_sequence 201304LETH_DMARDLAR_SRL_Pos (0U)RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)SHIFT_TAB_CCxPRCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_MskETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)PTRDIFF_MINGPIO_AFRH_AFSEL9_3 0x00000080UETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)_GLIBCXX_HAVE_SYS_TYPES_H 1CAN_F4R1_FB24 CAN_F4R1_FB24_MskCAN_F12R1_FB1 CAN_F12R1_FB1_MskRCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)USB_OTG_GOTGINT_HNSSCHG_Pos (9U)ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)EXTI_PR_PR11_Pos (11U)DWT_CTRL_CPIEVTENA_Pos 17U__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)MPU_TYPE_SEPARATE_Pos 0UUSB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)ETH_DMASR_RPS ETH_DMASR_RPS_MskGPIO_LCKR_LCK4 GPIO_LCKR_LCK4_MskRTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)GPIO_AFRH_AFSEL8_1 0x00000002URCC_APB1ENR_SPI3EN_Pos (15U)FSMC_BWTR3_ACCMOD_Pos (28U)RTC_ALRMBR_MNU_Pos (8U)_GLIBCXX_STD_C stdBKP4RUSB_OTG_HPRT_PCSTS_Pos (0U)traceSTREAM_BUFFER_SEND(xStreamBuffer,xBytesSent) USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_MskRCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)RCC_APB1RSTR_TIM14RST_Pos (8U)RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_MskADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)CAN_F0R1_FB15 CAN_F0R1_FB15_Msk_GLIBCXX11_USE_C99_COMPLEX 1CAN_F3R2_FB26_Pos (26U)__ULACCUM_FBIT__ 32EXTI_PR_PR8_Pos (8U)DCMI_CR_JPEG DCMI_CR_JPEG_MskRESERVED0RESERVED1RESERVED2RESERVED3RESERVED4RESERVED5RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)RESERVED7ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)UINT_LEAST8_MAX __UINT_LEAST8_MAX__RCC_AHB1ENR_GPIOIEN_Pos (8U)USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)EXTICRADC_BASE ADC123_COMMON_BASEADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000UADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk__aligned(x) __attribute__((__aligned__(x)))CAN2_SCE_IRQnRCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)CAN_FS1R_FSC15_Pos (15U)DWT_FUNCTION_DATAVADDR1_Pos 16UCAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)GPIO_MODER_MODE4 0x00000300UCAN_F10R1_FB6_Pos (6U)EXTI_FTSR_TR16 EXTI_FTSR_TR16_MskCAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)WWDG_SR_EWIF_Pos (0U)GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0CAN_TDT1R_TIME_Pos (16U)TIM_CR1_CKD TIM_CR1_CKD_MskCAN_F6R1_FB21_Pos (21U)EXTI_EMR_MR6_Pos (6U)USB_OTG_DIEPCTL_USBAEP_Pos (15U)RCC_APB2ENR_ADC3EN_Pos (10U)LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK)FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_MskCAN_F12R2_FB25 CAN_F12R2_FB25_MskSPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)EXTI_RTSR_TR2 EXTI_RTSR_TR2_MskRCC_CFGR_SWS_Pos (2U)CAN_F1R1_FB12_Pos (12U)ADC_SQR3_SQ2_Pos (5U)ARM_MPU_RBAR(Region,BaseAddress) (((BaseAddress) & MPU_RBAR_ADDR_Msk) | ((Region) & MPU_RBAR_REGION_Msk) | (MPU_RBAR_VALID_Msk))RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_MskFSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)CAN_F13R1_FB5_Pos (5U)__SIZEOF_POINTER__ 4SPI_SR_MODF SPI_SR_MODF_MskDAC_CR_MAMP2_Pos (24U)RCC_AHB2RSTR_DCMIRST_Pos (0U)RCC_SSCGR_MODPER RCC_SSCGR_MODPER_MskRCC_CR_HSION RCC_CR_HSION_MskCAN_F9R1_FB9_Pos (9U)ADC_SR_JEOC_Pos (2U)_RETARGETABLE_LOCKING 1RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)PTRDIFF_MAX __PTRDIFF_MAX__xQueueSend(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)LL_TIM_CCDMAREQUEST_CC 0x00000000UDMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)CAN_F8R2_FB25 CAN_F8R2_FB25_MskINT_FAST64_MAX __INT_FAST64_MAX__ETH_MACCR_JD ETH_MACCR_JD_MskRCC_CIR_PLLRDYIE_Pos (12U)CAN_F1R2_FB20 CAN_F1R2_FB20_MskADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)_SYS__TYPES_H I2C_CR1_ENARP I2C_CR1_ENARP_MskGPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)ETH_MACFFR_DAIF ETH_MACFFR_DAIF_MskETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_MskCAN_RDH0R_DATA4_Pos (0U)SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk__has_extension __has_featureCAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)USB_OTG_DPID_Pos (15U)ETH_MACMIIAR_CR_Pos (2U)EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)RTC_ALRMBR_HT RTC_ALRMBR_HT_MskLL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0CAN_F7R1_FB8 CAN_F7R1_FB8_MskEXTI1_IRQnADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)__ARM_FEATURE_COPROC 15__ULLACCUM_FBIT__ 32RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk__DECIMAL_DIG__ 17CAN_F8R1_FB25_Pos (25U)USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)EXTI_SWIER_SWIER21_Pos (21U)GPIO_OSPEEDR_OSPEED10_1 0x00200000URCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_MskCAN_TI1R_TXRQ CAN_TI1R_TXRQ_MskUSB_OTG_EPNUM_Pos (0U)GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)FSMC_BTR2_CLKDIV_Pos (20U)_REENT_CHECK_ASCTIME_BUF(ptr) _GLIBCXX_BITS_UNIFORM_INT_DIST_H STREAM_BUFFER_H CAN_F2R1_FB3_Pos (3U)CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)SDIO_MASK_TXFIFOFIE_Pos (16U)__INT8_MAX__ 0x7fCAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)__cpp_runtime_arrays 198712LEXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)CAN_F4R2_FB16 CAN_F4R2_FB16_MskDBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_MskUSART_SR_LBD_Pos (8U)_SYS_REENT_H_ CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)ETH_DMASR_RPS_Pos (17U)FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_MskEXTI_RTSR_TR6 EXTI_RTSR_TR6_MskRCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)DMA_SxCR_DMEIE DMA_SxCR_DMEIE_MskCAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)CAN_F8R1_FB19 CAN_F8R1_FB19_Msk__glibcxx_requires_heap_pred(_First,_Last,_Pred) ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400UCAN_F7R2_FB11_Pos (11U)SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)CAN_F9R1_FB1 CAN_F9R1_FB1_MskADC_SMPR1_SMP10 ADC_SMPR1_SMP10_MskGPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)CAN_F8R2_FB1 CAN_F8R2_FB1_MskIS_UART_HALFDUPLEX_INSTANCE IS_UART_INSTANCECAN_F0R1_FB12_Pos (12U)FSMC_SR2_FEMPT_Pos (6U)CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)I2C_CR1_ACK I2C_CR1_ACK_MskCAN_RDL0R_DATA0 CAN_RDL0R_DATA0_MskCAN_F12R2_FB4_Pos (4U)CAN_F10R2_FB27_Pos (27U)ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_MskGPIO_BSRR_BS15 0x00008000USPI_SR_MODF_Pos (5U)FLASH_OPTCR_RDP FLASH_OPTCR_RDP_MskCAN_F4R1_FB31 CAN_F4R1_FB31_MskDMA_LIFCR_CTEIF1_Pos (9U)CAN_F10R2_FB10 CAN_F10R2_FB10_MskI2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_MskCAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)INCLUDE_vTaskDelete 1pdFREERTOS_ERRNO_ENOTCONN 128RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_MskRTC_CR_ALRBIE_Pos (13U)LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2)EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_MskLL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)CAN_F9R1_FB0_Pos (0U)CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)CAN_F9R2_FB21_Pos (21U)GPIO_MODER_MODE8_1 0x00020000UFSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk__gnu_cxx__cpp_namespace_attributes 201411LCAN_F1R1_FB11_Pos (11U)LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)_REENT_LOCALE(_ptr) ((_ptr)->_locale)__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1ETH_DMAIER_AISE ETH_DMAIER_AISE_MskCAN_F11R2_FB5_Pos (5U)SPI_I2SCFGR_I2SCFG_Pos (8U)LL_AHB1_GRP1_ReleaseResetETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_MskLL_GPIO_PIN_0 GPIO_BSRR_BS_0EXTI_EMR_MR2 EXTI_EMR_MR2_MskGPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0UINT_LEAST16_MAX __UINT_LEAST16_MAX__EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)FSMC_PMEM4_MEMHOLD4_Pos (16U)CAN_F7R2_FB9_Pos (9U)CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)__FLT_MAX_EXP__ 128RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_MskUSART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)CAN_F12R1_FB26 CAN_F12R1_FB26_MskCAN_F0R1_FB22 CAN_F0R1_FB22_MskFSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)RCC_APB2ENR_ADC1EN_Pos (8U)SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)_PSTL_ASSERT_MSG(_Condition,_Message) __glibcxx_assert(_Condition)_GLIBCXX_HAVE_FLOAT_H 1GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)FSMC_BCR2_MTYP FSMC_BCR2_MTYP_MskRCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)CAN_F9R2_FB24 CAN_F9R2_FB24_MskCAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)USB_OTG_DOEPMSK_XFRCM_Pos (0U)portARCH_NAME NULLCAN_F3R2_FB29 CAN_F3R2_FB29_MskFSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)_GLIBCXX_LONG_DOUBLE_ALT128_COMPATGPIO_PUPDR_PUPD6_0 0x00001000UFSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)ADC_SQR1_SQ14_Pos (5U)CAN_F3R1_FB21_Pos (21U)TAMP_STAMP_IRQnGPIO_OSPEEDR_OSPEED10 0x00300000U__BKPT(value) __ASM volatile ("bkpt "#value)DMA_SxCR_MINC DMA_SxCR_MINC_MskSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)_GLIBCXX_HAVE_POWF 1CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_MskETH_MACFCR_PLT_Minus4 0x00000000UFSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_MskETH_DMASR_TPSS_Pos (1U)_GLIBCXX_WEAK_DEFINITION CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)__cust_iswap__CHAR16_TYPE__ short unsigned intDMA_LISR_DMEIF0 DMA_LISR_DMEIF0_MskRCC_CR_HSITRIM_Pos (3U)ETH_MACFFR_BFD ETH_MACFFR_BFD_MskSDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_MskCAN_F5R1_FB6_Pos (6U)ADC_SMPR1_SMP10_Pos (0U)FSMC_SR2_ILS_Pos (1U)GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)USB_OTG_GOTGCTL_SRQSCS_Pos (0U)GPIO_AFRL_AFSEL4 0x000F0000UCAN_F5R1_FB14_Pos (14U)RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)DMA_HISR_TEIF6 DMA_HISR_TEIF6_MskCAN_FA1R_FACT26 CAN_FA1R_FACT26_MskCAN_F0R2_FB3_Pos (3U)configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)CAN_F5R2_FB15 CAN_F5R2_FB15_MskADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)delaySPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_MskUSB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)FLASH_CR_MER FLASH_CR_MER_MskTIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)CAN_F0R1_FB31_Pos (31U)ETH_DMACHRBAR_HRBAP_Pos (0U)RCC_CIR_LSIRDYF_Pos (0U)CoreDebug_DEMCR_VC_BUSERR_Pos 8UUSB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)ITM_LSR_ByteAcc_Pos 2USDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)SYSCFG_EXTICR1_EXTI0_PH 0x00000007UFSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk__SIZEOF_INT__ 4ADC_CDR_DATA1_Pos (0U)ulTaskNotifyValueClearIndexed(xTask,uxIndexToClear,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )I2C_CR1_PE I2C_CR1_PE_MskDWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)TIM_SR_TIF TIM_SR_TIF_MskGPIO_AFRH_AFSEL13 0x00F00000UFSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)TIM_EGR_TG_Pos (6U)__INT32_MAX__ 0x7fffffffLCAN_F5R1_FB25_Pos (25U)FSMC_BCR4_WAITCFG_Pos (11U)FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)DAC_CR_MAMP2 DAC_CR_MAMP2_MskLL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0__cpp_inline_variables 201606LxPSR_V_Msk (1UL << xPSR_V_Pos)CAN_F3R1_FB5 CAN_F3R1_FB5_MskSPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)RNG_SR_DRDY RNG_SR_DRDY_MskTIM_CR2_OIS4 TIM_CR2_OIS4_MskFSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)USB_OTG_HPRT_PPWR_Pos (12U)TIM_CR1_URS_Pos (2U)PWR_CR_PDDS PWR_CR_PDDS_MskHISRCAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)DCMI_IER_FRAME_IE_Pos (0U)SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_MskCAN_F13R1_FB10 CAN_F13R1_FB10_MskI2C2_BASE (APB1PERIPH_BASE + 0x5800UL)_ZN5crash5panicEPKcerrCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )SPI_SR_FRE_Pos (8U)SPI_CR1_SSI SPI_CR1_SSI_MskUSB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)SYSCFG_EXTICR2_EXTI6_PF 0x00000500U__cplusplus 202002LCAN_MCR_DBF CAN_MCR_DBF_Msk__ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cnameETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U__glibcxx_assert(cond) do { __glibcxx_constexpr_assert(cond); } while (false)LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTHCAN_F5R1_FB19_Pos (19U)GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1TIM_EGR_BG_Pos (7U)FLASH_ACR_LATENCY_3WS 0x00000003U__glibcxx_requires_sorted_pred(_First,_Last,_Pred) DWT_FUNCTION_DATAVMATCH_Pos 8UPWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)CAN_F0R2_FB22_Pos (22U)USB_OTG_HPRT_PCDET_Pos (1U)CAN_F7R2_FB0_Pos (0U)SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)SYSCFG_EXTICR2_EXTI4_PI 0x00000008UDWT_CTRL_NOPRFCNT_Pos 24UGPIO_MODER_MODER2_Pos (4U)USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_MskTIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)CAN_F2R1_FB7 CAN_F2R1_FB7_MskCAN_F4R2_FB11_Pos (11U)CAN_F10R1_FB11 CAN_F10R1_FB11_MskUSB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)CAN_F1R2_FB7 CAN_F1R2_FB7_MskETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_MskGPIO_LCKR_LCK10_Pos (10U)GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)__gnu_debugADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)TaskHolder<512>ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)USART_CR1_TCIE USART_CR1_TCIE_MskGPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)GPIO_LCKR_LCKK GPIO_LCKR_LCKK_MskETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)CAN_F8R1_FB26 CAN_F8R1_FB26_MskRCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk___int_least32_t_defined 1RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)CAN_F1R1_FB21 CAN_F1R1_FB21_MskCAN_F7R1_FB29_Pos (29U)CAN_RDT1R_TIME_Pos (16U)SDIO_STA_RXOVERR SDIO_STA_RXOVERR_MskCAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)CAN_F11R1_FB6_Pos (6U)SYSCFG_EXTICR4_EXTI14_PB 0x00000100UEXTI_EMR_MR21_Pos (21U)__cpp_nontype_template_parameter_class 201806LCAN_F4R2_FB28 CAN_F4R2_FB28_MskDMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_MskUSB_OTG_HFNUM_FTREM_Pos (16U)GPIO_PUPDR_PUPD6_1 0x00002000UINT_FAST64_MIN (-INT_FAST64_MAX - 1)traceTASK_RESUME_FROM_ISR(pxTaskToResume) TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)CAN_F0R2_FB9 CAN_F0R2_FB9_MskCAN_F2R2_FB9_Pos (9U)CAN_F12R2_FB2 CAN_F12R2_FB2_MskTIM3_BASE (APB1PERIPH_BASE + 0x0400UL)CAN_F6R2_FB21_Pos (21U)USART_CR1_M USART_CR1_M_MskCAN_F2R2_FB21 CAN_F2R2_FB21_MskUSB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)dma_finishRNG_CR_IE_Pos (3U)__FLT32_MIN_EXP__ (-125)LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)_T_WCHAR_ TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)SysTick_IRQnETH_MMCRFCECR_RFCEC_Pos (0U)__LFRACT_MAX__ 0X7FFFFFFFP-31LRCAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)__USACCUM_MIN__ 0.0UHKFLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)ETH_DMAOMR_TTC_64Bytes 0x00000000UI2C_CR2_DMAEN I2C_CR2_DMAEN_MskLL_TIM_CHANNEL_CH1 TIM_CCER_CC1ECAN_F4R1_FB17 CAN_F4R1_FB17_MskDMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)CAN_F6R2_FB15_Pos (15U)_GLIBCXX_MAKE_MOVE_ITERATOR(_Iter) std::make_move_iterator(_Iter)SDIO_CMD_CEATACMD_Pos (14U)RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)RTC_BKP10R RTC_BKP10R_MskCAN_F10R1_FB16_Pos (16U)CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)pdFREERTOS_ERRNO_ENOBUFS 105SDIO_STA_CMDSENT_Pos (7U)RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)__FLT64_HAS_DENORM__ 1USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_MskINT_LEAST16_MIN__cpp_binary_literals 201304LRTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)TaskHolder<256>FSMC_PCR4_PWID_Pos (4U)USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)GPIO_OSPEEDR_OSPEED13_1 0x08000000UFSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)CAN_F0R1_FB4_Pos (4U)USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)__need_size_t CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk__CMSIS_GCC_RW_REG(r) "+r" (r)FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)RCC_APB2RSTR_USART1RST_Pos (4U)TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)TIM_EGR_CC3G TIM_EGR_CC3G_MskUSB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_MskEXTI_IMR_MR18_Pos (18U)CAN_F9R2_FB31 CAN_F9R2_FB31_MskRTC_BKP6R RTC_BKP6R_MskCAN_FFA1R_FFA7_Pos (7U)GPIOE ((GPIO_TypeDef *) GPIOE_BASE)CCMR1SDIO_ICR_CCRCFAILC_Pos (0U)FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)EXTI_PR_PR13 EXTI_PR_PR13_Msk_ZN6tskmem10TaskHolderILj256EE6createEPFvPvEPKcS2_mUSB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_MskUSB_OTG_DIEPCTL_EPTYP_Pos (18U)RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_MskportBYTE_ALIGNMENT 8CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)CAN_F8R2_FB25_Pos (25U)LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASKETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)_GLIBCXX_END_NAMESPACE_LDBL_OR_CXX11 _GLIBCXX_END_NAMESPACE_CXX11GPIO_AFRL_AFSEL7_0 0x10000000UCAN_F0R1_FB15_Pos (15U)CAN_MCR_RESET CAN_MCR_RESET_MskCAN_F12R1_FB26_Pos (26U)LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)__GNUCLIKE_BUILTIN_NEXT_ARG 1DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_MskCAN_F8R2_FB31_Pos (31U)traceMOVED_TASK_TO_READY_STATE(pxTCB) GPIO_AFRH_AFSEL15_0 0x10000000UADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)__cpp_lib_ranges 202110LADC_CR2_EXTSEL_Pos (24U)SYSCFG_EXTICR1_EXTI1_PH 0x00000070UUI_BUTTON_PERIPH LL_AHB1_GRP1_PERIPH_GPIOADMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_MskTIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)FLASH_BASE 0x08000000ULFSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)CAN_FA1R_FACT0_Pos (0U)pdFREERTOS_ERRNO_ENOTDIR 20RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)EXTI_EMR_EM3 EXTI_EMR_MR3tskKERNEL_VERSION_MAJOR 10LL_UTILS_HSEBYPASS_OFF 0x00000000USDIO_CMD_SDIOSUSPEND_Pos (11U)USART_CR2_CPOL USART_CR2_CPOL_MskFSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)_REENT_INIT_RESERVED_0 TypeChangeTempCAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)__N(msgid) (msgid)CAN_F8R2_FB19_Pos (19U)ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_MskGPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_MskFLASH_ACR_LATENCY_7WS 0x00000007UUSB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_MskADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)_GLIBCXX23_DEPRECATED CAN_F0R1_FB0 CAN_F0R1_FB0_MskCAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_MskCAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)__cpp_lib_is_invocable 201703L__FLT32X_MAX_EXP__ 1024GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)CAN_IER_SLKIE_Pos (17U)EXTI_RTSR_TR9_Pos (9U)ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)CAN_F11R2_FB12_Pos (12U)RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)FSMC_SR3_FEMPT_Pos (6U)RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_MskCAN_F7R1_FB1_Pos (1U)RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_MskFSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)TIM_DIER_CC4DE TIM_DIER_CC4DE_MskETH_MACRWUFFR_D_Pos (0U)CAN_F9R1_FB25 CAN_F9R1_FB25_MskDCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)RCC_APB2RSTR_TIM8RST_Pos (1U)CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk_GLIBCXX_HAVE_MODFF 1USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk_HAVE_INITFINI_ARRAY 1configUSE_RECURSIVE_MUTEXES 1USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)GPIO_AFRL_AFSEL7_2 0x40000000UGPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk__MPU_PRESENT 1UCAN_F2R1_FB19_Pos (19U)CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)CAN_FM1R_FBM25_Pos (25U)GPIO_AFRH_AFSEL15_2 0x40000000UDMA1_Stream1_IRQnresolve_symbolsDAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)CAN_F5R1_FB23_Pos (23U)_ZN6tskmem10TaskHolderILj176EE6createEPFvPvEPKcS2_mLL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMENCAN_TI1R_IDE CAN_TI1R_IDE_MskFSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)I2C_OAR1_ADD6_Pos (6U)CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK)_WIDE_ORIENT 1USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)__glibcxx_requires_sorted_set_pred(_First1,_Last1,_First2,_Pred) SYSCFG_EXTICR3_EXTI10_PE 0x00000400USPI3_IRQnETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_MskDMA_HISR_HTIF4_Pos (4U)FSMC_BWTR4_DATAST_5 (0x20UL << FSMC_BWTR4_DATAST_Pos)GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1ETH_MACFFR_BFD_Pos (5U)CAN_FM1R_FBM19_Pos (19U)EXTI_EMR_EM10 EXTI_EMR_MR10RCC_APB1LPENR_SPI2LPEN_Pos (14U)FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE CAN_FFA1R_FFA27_Pos (27U)TIM_CR2_OIS2 TIM_CR2_OIS2_MskCAN_F5R1_FB16 CAN_F5R1_FB16_MskCAN_TDL1R_DATA3 CAN_TDL1R_DATA3_MskconfigMAX_TASK_NAME_LEN (8)ETH_MACCR_APCS_Pos (7U)RTC_CR_TSE_Pos (11U)USB_OTG_DAINTMSK_IEPM_Pos (0U)FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_MskSPI_SR_FRE SPI_SR_FRE_MskCAN_F13R2_FB16_Pos (16U)USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_MskDMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_MskARM_MPU_AP_URO 2UETH_DMABMR_PBL_1Beat 0x00000100USDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)LRU_H ADC_CSR_STRT3_Pos (20U)GPIO_MODER_MODE1_1 0x00000008UETH_MACA1HR_MBC_LBits31_24 0x08000000UINCLUDE_xTaskGetHandle 0CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)EXTI_EMR_EM14 EXTI_EMR_MR14USB_OTG_HCCHAR_CHENA_Pos (31U)USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)TIM_CCER_CC1NE TIM_CCER_CC1NE_MskRTC_TSDR_DU RTC_TSDR_DU_MskCAN_F11R2_FB15 CAN_F11R2_FB15_MskCAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk_LDBL_EQ_DBL 1RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)RTC_ISR_RSF RTC_ISR_RSF_MskUSB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk_GCC_SIZE_T USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)__SIZEOF_SIZE_T__ 4FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)NVIC_USER_IRQ_OFFSET 16CAN_TSR_LOW_Pos (29U)CAN_F3R2_FB15_Pos (15U)RCC_CSR_LSION RCC_CSR_LSION_MskRTC_WPR_KEY RTC_WPR_KEY_MskCAN_F1R2_FB22_Pos (22U)FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUSI2C_CR1_ENARP_Pos (4U)RTC_ALRMBR_MSK4_Pos (31U)FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)DMA_HISR_DMEIF7_Pos (24U)DCMI_CR_CROP_Pos (2U)DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk_GLIBCXX_HAVE_ATOMIC_LOCK_POLICY 1CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)GPIO_PUPDR_PUPD14 0x30000000URTC_ISR_ALRBWF_Pos (1U)ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_MskCAN_FM1R_FBM25 CAN_FM1R_FBM25_MskUSB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk__cpp_variadic_templates 200704LCAN_F10R1_FB29 CAN_F10R1_FB29_Msk__LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__,__STREAM__) ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : DMA2_Stream7)TIM_CCR2_CCR2 TIM_CCR2_CCR2_MskOPTKEYRCAN_FFA1R_FFA13 CAN_FFA1R_FFA13_MskETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)CAN_F13R1_FB23_Pos (23U)GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)__cpp_lib_concepts 202002LNVIC_SRV_RXE_CLRF LL_DMA_ClearFlag_TE1_WCHAR_T_DEFINED SYSCFG_EXTICR4_EXTI14_PC 0x00000200UFSMC_BCR2_WAITCFG_Pos (11U)RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_MskCAN_F6R2_FB21 CAN_F6R2_FB21_MskI2C_OAR1_ADD6 I2C_OAR1_ADD6_MskCAN_F0R2_FB26 CAN_F0R2_FB26_MskconfigPRECONDITION_DEFINED 0CAN_F6R1_FB10_Pos (10U)FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)EXTI_FTSR_TR13_Pos (13U)_FSEEK_OPTIMIZATION 1ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)DMA_HISR_HTIF7 DMA_HISR_HTIF7_MskADC_CCR_MULTI ADC_CCR_MULTI_MskGPIO_ODR_OD0 0x00000001UETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)TIM_CCMR2_OC4FE_Pos (10U)USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)ETH_DMAOMR_RSF ETH_DMAOMR_RSF_MskADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)CAN_F5R2_FB1_Pos (1U)FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)ADC_SQR3_SQ3_Pos (10U)___int_least64_t_defined 1GPIO_BSRR_BS8 0x00000100UARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)__offsetof(type,field) offsetof(type, field)CAN_F11R2_FB12 CAN_F11R2_FB12_MskETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)_READ_WRITE_BUFSIZE_TYPE intETH_DMAIER_TIE_Pos (0U)CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_MskUSB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_MskRTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)CAN_FS1R_FSC21_Pos (21U)__cpp_lib_is_null_pointer 201309LEXTI_FTSR_TR21 EXTI_FTSR_TR21_MskETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk__INT32_C(c) c ## LADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)TIM_SR_CC4IF_Pos (4U)CAN_F5R2_FB19_Pos (19U)_GLIBCXX_USE_C99_MATH _GLIBCXX11_USE_C99_MATHGPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1RCC_AHB1RSTR_GPIOFRST_Pos (5U)CAN_F12R1_FB18 CAN_F12R1_FB18_MskEXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == UART4) || ((INSTANCE) == UART5) || ((INSTANCE) == USART6))uint64_tCAN_F8R1_FB20_Pos (20U)SYSCFG_EXTICR2_EXTI7_PE 0x00004000UINT_FAST8_MAX __INT_FAST8_MAX__CAN_F12R2_FB30 CAN_F12R2_FB30_MskCAN_F8R2_FB0_Pos (0U)CAN_F2R2_FB12 CAN_F2R2_FB12_MskLL_DMA_MEMORY_NOINCREMENT 0x00000000UCAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)xQueueSendToBack(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )ETH_DMAIER_ETIE_Pos (10U)CAN_F7R1_FB22_Pos (22U)CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_MskLL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUTCAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)CAN_F11R2_FB3 CAN_F11R2_FB3_MskRTC_BKP6R_Pos (0U)FSMC_SR2_IREN FSMC_SR2_IREN_MskRTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_MskGPIO_OTYPER_OT13 0x00002000URCC_APB2ENR_SPI1EN_Pos (12U)TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)EXTI_IMR_IM5 EXTI_IMR_MR5CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)CAN_F11R1_FB11_Pos (11U)FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)CAN_F8R1_FB14_Pos (14U)__FINITE_MATH_ONLY__ 0DWT_CTRL_CYCEVTENA_Pos 22U__no_lock_analysis __lock_annotate(no_thread_safety_analysis)EXTI_SWIER_SWIER10_Pos (10U)GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1__ATOMIC_CONSUME 1_PSTL_PAR_BACKEND_SERIAL CAN_F7R2_FB29_Pos (29U)GPIO_OTYPER_OT14 0x00004000UIWDG ((IWDG_TypeDef *) IWDG_BASE)EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0SDIO_MASK_TXACTIE_Pos (12U)DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)GPIO_ODR_ODR_0 GPIO_ODR_OD0RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)__glibcxx_requires_sorted(_First,_Last) CAN_F11R1_FB13 CAN_F11R1_FB13_MskUSB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_MskUSB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_MskUSB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)TIM_DIER_CC3IE TIM_DIER_CC3IE_MskRTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)__cpp_lib_math_constants 201907LI2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)_GLIBCXX_HAVE_MBSTATE_T 1_GLIBCXX_BEGIN_NAMESPACE_CXX11 namespace __cxx11 {RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM5) || ((INSTANCE) == TIM8))__pt_guarded_by(x) __lock_annotate(pt_guarded_by(x))USB_OTG_CHNUM USB_OTG_CHNUM_MskDAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_MskRTC_CR_BCK RTC_CR_BKPCAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)RCC_APB1RSTR_TIM12RST_Pos (6U)APSR_N_Pos 31UCAN_FA1R_FACT18_Pos (18U)traceSTREAM_BUFFER_RESET(xStreamBuffer) ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_MskCAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)TIM_SR_CC4IF TIM_SR_CC4IF_MskRTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)EXTI_RTSR_TR7 EXTI_RTSR_TR7_MskCAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)__LLFRACT_IBIT__ 0CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)__ULFRACT_FBIT__ 32ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)CAN_F11R2_FB20 CAN_F11R2_FB20_MskCAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_MskDCMI_DR_BYTE3 DCMI_DR_BYTE3_MskLL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_MskRTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)QUEUE_H CAN_F5R2_FB5_Pos (5U)USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_MskLL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)GPIO_BSRR_BR13 0x20000000UGPIO_IDR_ID12 0x00001000UUSB_OTG_DIEPDMA_DMAADDR_Pos (0U)IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3) || ((INSTANCE) == USART6))ITM_LSR_Present_Pos 0UCAN_F13R2_FB6 CAN_F13R2_FB6_MskUSB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_MskDMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk__INT_LEAST8_MAX__ 0x7f__INTPTR_WIDTH__ 32CAN_F1R2_FB25 CAN_F1R2_FB25_MskEXTI_IMR_MR2 EXTI_IMR_MR2_MskCAN_F9R2_FB10_Pos (10U)ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_MskLL_DMA_FIFOTHRESHOLD_1_4 0x00000000USPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk__DBL_DENORM_MIN__ double(4.9406564584124654e-324L)TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)DAC_DHR12R2_DACC2DHR_Pos (0U)CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)CAN_F13R1_FB11_Pos (11U)ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)CAN_F12R2_FB26_Pos (26U)USB_OTG_HCCHAR_MC_Pos (20U)SCB_DFSR_VCATCH_Pos 3UFSMC_PCR3_PWAITEN_Pos (1U)CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk__containerof(x,s,m) ({ const volatile __typeof(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)SCB_CCR_NONBASETHRDENA_Pos 0UWWDG_CFR_W3 WWDG_CFR_W_3USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)AFSRGPIO_LCKR_LCK0_Pos (0U)ADC_CSR_STRT1 ADC_CSR_STRT1_MskCAN_TDH0R_DATA5_Pos (8U)_ZN5crash6Matrix12dma_finishedEvCAN_MCR_INRQ CAN_MCR_INRQ_MskCAN_F5R1_FB2_Pos (2U)CAN_F3R1_FB8 CAN_F3R1_FB8_MskCAN_F1R1_FB14 CAN_F1R1_FB14_MskFSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)GPIO_AFRH_AFSEL12_3 0x00080000UCAN_F10R2_FB14_Pos (14U)DWT_CTRL_SLEEPEVTENA_Pos 19UGPIO_AFRL_AFSEL1_3 0x00000080UCAN_FFA1R_FFA3 CAN_FFA1R_FFA3_MskETH_DMASR_RPSS ETH_DMASR_RPSS_MskCAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)TIM_SR_TIF_Pos (6U)CAN_F7R1_FB23 CAN_F7R1_FB23_MskETH_MACA2HR_MBC_LBits15_8 0x02000000URCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk__UFRACT_MAX__ 0XFFFFP-16URFSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)OTG_HS_EP1_IN_IRQnCAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)SrcAddressCAN_TSR_RQCP2_Pos (16U)TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)CAN_F11R2_FB0_Pos (0U)ETH_DMAOMR_SR_Pos (1U)USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_MskDMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)USB_OTG_DSTS_FNSOF_Pos (8U)CAN_F8R1_FB1_Pos (1U)ETH_DMAOMR_FUGF_Pos (6U)USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)_PSTL_UDS_PRESENT (__INTEL_COMPILER >= 1900 && __INTEL_COMPILER_BUILD_DATE >= 20180626)DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MISCAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)CAN_F8R1_FB3 CAN_F8R1_FB3_MskTIM6_DAC_IRQnCAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)ETH_MACCR_IFG_48Bit 0x000C0000UTIM_CCMR2_CC4S TIM_CCMR2_CC4S_MsktraceSTART() _GLIBCXX_INLINE_VERSION 0RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_MskCAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)__need_wint_tFSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)configENABLE_FPU 1USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)CAN_F0R2_FB26_Pos (26U)SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)EXTI_FTSR_TR1 EXTI_FTSR_TR1_MskETH_DMASR_RBUS ETH_DMASR_RBUS_MskRCC_APB2ENR_TIM9EN_Pos (16U)CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)taskEXIT_CRITICAL() portEXIT_CRITICAL()GPIO_OSPEEDR_OSPEED11 0x00C00000URNG_SR_CEIS_Pos (5U)CAN_FA1R_FACT18 CAN_FA1R_FACT18_MskUSB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)CAN_F4R1_FB23 CAN_F4R1_FB23_MskRCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_MskFSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)ADC_SR_AWD ADC_SR_AWD_MskUSB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_MskRCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)_REENT_CHECK_RAND48(ptr) USB_OTG_DOEPMSK_OPEM_Pos (8U)__LDBL_HAS_QUIET_NAN__ 1TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)CAN_F7R1_FB5 CAN_F7R1_FB5_MskEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)RCC_CIR_CSSC_Pos (23U)SYSCFG_EXTICR4_EXTI13_Pos (4U)FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)TIM_CR2_OIS2N_Pos (11U)IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)NVIC_GetVector __NVIC_GetVectorCAN_F6R2_FB5 CAN_F6R2_FB5_Msk__used __attribute__((__used__))__END_DECLS }FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)ETH_DMAOMR_RSF_Pos (25U)RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)CAN_TDH0R_DATA7_Pos (24U)ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)UART_DMA_RX_Stream LL_DMA_STREAM_1ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_MskCAN_BTR_SILM_Pos (31U)__SIZEOF_SHORT__ 2DMA_SxCR_PINC_Pos (9U)tskKERNEL_VERSION_MINOR 4CAN_F12R2_FB12_Pos (12U)DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk__LDBL_IS_IEC_60559__ 1traceQUEUE_DELETE(pxQueue) ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)ETH_DMASR_EBS_DescAccess_Pos (25U)CAN_FA1R_FACT25_Pos (25U)CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk__LDBL_MAX__ 1.7976931348623157e+308LADC_SMPR2_SMP3 ADC_SMPR2_SMP3_MskLL_AHB1_GRP1_ForceResetRTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)CAN_F6R1_FB22 CAN_F6R1_FB22_MskETH_DMABMR_DA ETH_DMABMR_DA_MskTIM_CCMR1_OC1M_Pos (4U)CAN_F11R1_FB26 CAN_F11R1_FB26_MskUSB_OTG_HAINT_HAINT_Pos (0U)CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)GAMMA_TABLE 0,5457,29817,80516,162923,281458,439954,641840,890240,1188039,1537929,1942444,2403978,2924810,3507116,4152982,4864412,5643341,6491634,7411101,8403494,9470517,10613827,11835037,13135722,14517420,15981632,17529827,19163445,20883896,22692560,24590795,26579932,28661279,30836123,33105727,35471336,37934175,40495450,43156350,45918046,48781693,51748430,54819382,57995658,61278352,64668548,68167312,71775702,75494761,79325520,83269000,87326210,91498147,95785800,100190146,104712152,109352777,114112969,118993667,123995802,129120297,134368064,139740008,145237029,150860014,156609846,162487399,168493540,174629130,180895023,187292063,193821092,200482942,207278440,214208408,221273660,228475005,235813246,243289179,250903597,258657285,266551025,274585592,282761756,291080282,299541931,308147457,316897611,325793140,334834783,344023278,353359357,362843747,372477171,382260349,392193995,402278820,412515531,422904831,433447417,444143985,454995226,466001827,477164472,488483841,499960610,511595451,523389035,535342027,547455090,559728882,572164060,584761277,597521181,610444420,623531635,636783469,650200557,663783533,677533030,691449674,705534092,719786906,734208736,748800199,763561908,778494476,793598512,808874621,824323407,839945472,855741414,871711829,887857311,904178450,920675835,937350054,954201689,971231322,988439532,1005826897,1023393991,1041141387,1059069655,1077179363,1095471077,1113945361,1132602776,1151443882,1170469237,1189679396,1209074911,1228656336,1248424219,1268379107,1288521546,1308852080,1329371250,1350079596,1370977655,1392065965,1413345058,1434815468,1456477724,1478332356,1500379891,1522620853,1545055767,1567685153,1590509533,1613529424,1636745343,1660157806,1683767325,1707574412,1731579578,1755783331,1780186178,1804788625,1829591174,1854594329,1879798591,1905204457,1930812428,1956622997,1982636661,2008853912,2035275242,2061901143,2088732102,2115768607,2143011144,2170460198,2198116253,2225979790,2254051289,2282331231,2310820093,2339518352,2368426482,2397544959,2426874253,2456414837,2486167181,2516131754,2546309023,2576699454,2607303513,2638121662,2669154366,2700402085,2731865278,2763544406,2795439927,2827552295,2859881968,2892429398,2925195040,2958179346,2991382765,3024805748,3058448743,3092312198,3126396559,3160702271,3195229778,3229979524,3264951950,3300147498,3335566607,3371209715,3407077261,3443169682,3479487413,3516030888,3552800542,3589796806,3627020113,3664470893,3702149575,3740056589,3778192362,3816557321,3855151890,3893976496,3933031561,3972317509,4011834762,4051583739,4091564863,4131778550,4172225221,4212905291,4253819177,4294967295metrics/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/crash/mindraw.cpp_ZN5crash4draw6bitmapERNS_6MatrixEPKhhhhtth_ZN5crash4draw4textERNS_6MatrixEPKhtth_ZN4font10lcdpixel_64infoElcdpixel_6strideFONT_LCDPIXEL_6_H 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(*&&)(unsigned char))::&, dummy&&)::&>InputFunctor_ZN9gunzip_ns20DeflateDispatchFinalILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEDaS8_SA_SC_OT3__ZN9gunzip_ns17CreateHuffmanTreeILb0ELj303ELj9ERPFhjEEEbPKcRNS_17RandomAccessArrayILb0EXT0_EXT1_EEEjOT2_DEFLATE_ALLOCATION_AUTOMATIC _ZNK9gunzip_ns17RandomAccessArrayILb0ELj303ELj9EE3GetEjpacked_ZN9gunzip_ns20DeflateInputDispatchILh0ENS_5dummyEPFhvEPFbhEJEEEDaOT0_OT1_OT2_DpOT3__ZZN9gunzip_ns9GetBTableILb0EEEPKhvE4datauintmax_t_ZZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bENUljE_C4EOSA__ZN5crash6decode3spsEdummyFlag_NoTrackFlagMask__error_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUlhE_C4Ev_ZN9gunzip_ns12DeflateStateILb0EEC4Ev15FunctionalStateDeflAbortable_InFunLengthFunctorDeflateOutputDispatch<0, gunzip_ns::dummy, unsigned char (*)(), bool (*)(unsigned char)>_ZN5crash6decode19BackTraceParseStateC4Ev_ZN5crash6decode4btpsEOutputFunctor_Iftrue_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENKUlhE_clEhbacktrackElementSizeDeflAbortable_OutFun_ZN9gunzip_ns17RandomAccessArrayILb0ELj47ELj6EE4WSetILj128EEEvjy_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE_D4EvFail_If(condition) do { if(condition) return -1; } while(0)_ZN9gunzip_ns17RandomAccessArrayILb0ELj47ELj6EE4QSetEjhDebugDataconditionalunwind_amtMAX_WINDOW_SIZEnlen_ndist_ncode_ZN9gunzip_ns15DeflateBitCache8HuffReadILb0EPFhvELj47ELj6EEEmOT0_RNS_17RandomAccessArrayILb0EXT1_EXT2_EEEDeflateBitCacheBEGIN_COND(name) template struct name : public std::false_type {}; template struct name_ZN9gunzip_ns5lbaseEj_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUltjE_C4EOSC_rshift_ZN5crash6decode19apply_isr_unwind_toERmS1_S1_Gunzip<2, unsigned char (*)(), gunzip_ns::DeflateOutputDispatch<0, dummy, unsigned char (*)(), bool (*)(unsigned char)>(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&, gunzip_ns::DeflateOutputDispatch<0, dummy, unsigned char (*)(), bool (*)(unsigned char)>(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&, gunzip_ns::dummy>Backtrackable_ZN9gunzip_ns13DeflateWindowC2Ev__param1_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUlhE_D4Ev_ZN9gunzip_ns17RandomAccessArrayILb0ELj303ELj9EE4QSetEjt_ZN9gunzip_ns17CreateHuffmanTreeILb0ELj303ELj9ERZNS_12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bEUljE_EEbPKcRNS_17RandomAccessArrayILb0EXT0_EXT1_EEEjOT2_symbol_table_sizeget_backtableFloorLog2_ZN9gunzip_ns15DeflateBitCacheC2EvReadLengthRandomAccessArrayconditional_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENKUljE1_clEj_GLIBCXX_CSTDINT 1DeflDeclWindowndist (((nlen_ndist_ncode >> 5u) & 0x1Fu) + 1u)_ZNK9gunzip_ns17RandomAccessArrayILb0ELj15ELj9EE3GetEjBitCountDEFLATE_USE_DATA_TABLES _ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE_C4ERKSJ__ZN9gunzip_ns17RandomAccessArrayILb0ELj303ELj9EE3SetEjtRandomAccessArrayRandomAccessArray_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENKUltjE_clEtjOutputHelpernlenconditionalHuffRead(tree,target) auto p = state.template HuffRead(std::forward(input), tree); if((Abortable & Flag_InputAbortable) && !~p) return -2; target = pnumbitsacquiredCreateHuffmanTree::DynTreeFunc(unsigned char (*&&)(), uint_fast16_t, gunzip_ns::dummy&&, bool)::&>apply_isr_unwind_to_ZN9gunzip_ns17CreateHuffmanTreeILb0ELj47ELj6ERZNS_12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bEUljE_EEbPKcRNS_17RandomAccessArrayILb0EXT0_EXT1_EEEjOT2_dtree_fun_ZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_b_ZZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bENKUljE_clEjRandomAccessArray_ZNK5crash6decode9DebugData12get_symtableEvnum_valuesGetBitsCreateHuffmanTreeinfunnlen (((nlen_ndist_ncode >> 0u) & 0x1Fu) + 257u)10FlagStatusparam2_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE1_D4EvCreateHuffmanTree::DynTreeFunc(unsigned char (*&&)(), uint_fast16_t, gunzip_ns::dummy&&, bool)::&>ElemBits_ZN9gunzip_ns17RandomAccessArrayILb0ELj303ELj9EE4WSetILj192EEEvjyBacktrackFunctorUSE_BITARRAY_TEMPORARY_IN_HUFFMAN_CREATION_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE_C4EOSJ_END_CONDHuffRead_ZN9gunzip_ns17CreateHuffmanTreeILb0ELj47ELj6ERZNS_6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES3_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS4_ILh0ES5_S3_S7_EEDaS9_SB_SD_EUltjE_S5_EEiS9_SB_SD_OT3_EUljE_EEbPKcRNS_17RandomAccessArrayILb0EXT0_EXT1_EEEjSD_uint_least64_t__lenlenssignalDoneDeflateInputDispatch<0, gunzip_ns::dummy, unsigned char (*)(), bool (*)(unsigned char)>_ZN9gunzip_ns13DeflateWindowC4Ev_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE0_D4Evuint_least16_tDeflateStateCreateHuffmanTreeDeflatebt_maxlenFlag_TrackIn_Conddtree_ZN9gunzip_ns17RandomAccessArrayILb0ELj288ELj4EE4QSetEjh_ZN9gunzip_ns17RandomAccessArrayILb0ELj15ELj9EE3SetEjtDeflateDispatchFinal<2, unsigned char (*)(), gunzip_ns::DeflateOutputDispatch<0, dummy, unsigned char (*)(), bool (*)(unsigned char)>(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&, gunzip_ns::DeflateOutputDispatch<0, dummy, unsigned char (*)(), bool (*)(unsigned char)>(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&, gunzip_ns::dummy>WindowFunctornamebuf1namebuf2_ZN9gunzip_ns17CreateHuffmanTreeILb0ELj47ELj6ERPFhjEEEbPKcRNS_17RandomAccessArrayILb0EXT0_EXT1_EEEjOT2_WSet<192>RandomAccessArrayDeflateWindow_ZN9gunzip_ns5dbitsEjget_symtableassert(__e) ((void)0)__windowoutputcopyHuffRead_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUlhE_C4EOSC_dbits_ZN9gunzip_ns15DeflateBitCache7GetBitsILb0EPFhvEEEyOT0_jUSE_BITARRAY_FOR_LENGTHSuint_fast8_tlbitsndistDummyGetBits(numbits) do { auto p = state.template GetBits(std::forward(input), numbits); if((Abortable & Flag_InputAbortable) && !~p) return -2; } while(0)_ZN9gunzip_ns17RandomAccessArrayILb0ELj47ELj6EE3SetEjhDimensionBackTraceParseState_ZN9gunzip_ns17RandomAccessArrayILb0ELj15ELj5EE3SetEjh_ZN9gunzip_ns12OutputHelperILb1EE10outputcopyIRZNS_21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_EUltjE_EEbOT_Rtj_ZZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bENUljE_C4Evoutputcopy(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&>SymbolParseStateFail_IfCeilLog2_ZN9gunzip_ns15DeflateBitCacheC4Evuint_fast64_t__output__thisgunzip_nsskipdefBtFunuintptr_tlltree_funlocal_sps_Iffalse_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE0_4_FUNEj_ZN9gunzip_ns15DeflateBitCache8HuffReadILb0EPFhvELj303ELj9EEEmOT0_RNS_17RandomAccessArrayILb0EXT1_EXT2_EEElower_PCold_ptr_dbg_data_begin_ZNK9gunzip_ns17RandomAccessArrayILb0ELj288ELj4EE3GetEjBEGIN_CONDDISABLEprevious_idxHuffReadDeflateState_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUltjE_C4Ev_ZN9gunzip_ns9GetBTableILb0EEEPKhv_FUNGetBTable<>DummyGetBitsparse_stateinput_ZZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bENUljE_D4Ev_ZN9gunzip_ns12DeflateStateILb0EEC2Evuint_fast32_t_ZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2__Z7DeflateIJPFhvEPFbhEEEDaDpOT_RESEToutput(dummy&&, unsigned char (*&&)(), bool (*&&)(unsigned char))::&>_ZN9gunzip_ns12OutputHelperILb1EE6outputIRZNS_21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_EUlhE_EEbOT_h_ZN5crash6decode19BackTraceParseStateC2EvwhatDeflDeclWindow gunzip_ns::DeflateWindow window;local_btps_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENKUljE0_clEjGetBits(numbits,target) auto p = state.template GetBits(std::forward(input), numbits); if((Abortable & Flag_InputAbortable) && !~p) return -2; target = plencodeuint_least32_t_ZN5crash6decode15apply_unwind_toERmS1_S1_sStateTypeSmallestType_ZN9gunzip_ns17RandomAccessArrayILb0ELj15ELj9EE4QSetEjtFlag_OutputAbortable_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE1_4_FUNEjupper_PCdistcode_ZN9gunzip_ns5lbitsEj_ZN9gunzip_ns6rshiftEjresolved_ZN9gunzip_ns5dbaseEj_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUltjE_C4ERKSC_END_COND(name) , void>> : public std::true_type {}; template inline constexpr bool name ## _v = name::value;Lengthsbacktrace_length/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/crash/decode.cpp_ZZN9gunzip_ns12DeflateStateILb0EE11DynTreeFuncILb0EPFhvENS_5dummyEEEDaOT0_jOT1_bENUljE_C4ERKSA__ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENKUljE_clEj__get_CONTROLdbase_ZZN9gunzip_ns21DeflateOutputDispatchILh0ENS_5dummyEPFhvEPFbhEEEDaOT0_OT1_OT2_ENUltjE_D4Evuint_least8_tDynTreeFuncapply_unwind_to_ZNK5crash6decode9DebugData13get_backtableEvUSE_BITARRAY_FOR_HUFFNODES_ZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_currname_ZZN9gunzip_ns6GunzipILh2EPFhvERZNS_21DeflateOutputDispatchILh0ENS_5dummyES2_PFbhEEEDaOT0_OT1_OT2_EUlhE_RZNS3_ILh0ES4_S2_S6_EEDaS8_SA_SC_EUltjE_S4_EEiS8_SA_SC_OT3_ENUljE_C4EvcurraddrFlag_InputAbortable_ZN9gunzip_ns17RandomAccessArrayILb0ELj288ELj4EE3SetEjhuint_fast16_tLL_DMA_ClearFlag_TC5LL_DMA_ClearFlag_TE5HardFault_Handler_CrashLL_TIM_ClearFlag_UPDATETIM1_BRK_TIM9_IRQHandler_CrashDMA2_Stream5_IRQHandler_CrashLL_DMA_IsActiveFlag_TC5LL_DMA_IsActiveFlag_TE5LL_TIM_SetCounterLL_TIM_IsActiveFlag_UPDATELL_TIM_SetAutoReload/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/crash/isr.cpp__DBL_MAX__ ((double)1.7976931348623157e+308L)__DBL_NORM_MAX__ ((double)1.7976931348623157e+308L)__DBL_EPSILON__ ((double)2.2204460492503131e-16L)/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/libc/mem.c_dest__DBL_MIN__ ((double)2.2250738585072014e-308L)NULL ((void *)0)_srcGNU C17 13.3.1 20240614 -mthumb -mfloat-abi=soft -mcpu=cortex-m3 -march=armv7-m -ggdb3 -O3 -ffreestanding -fno-builtin__STDC_VERSION__ 201710L__DBL_DENORM_MIN__ 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((void)0U)__I volatile constIS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) || ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) || ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) || ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))__RBITpinposIS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) || ((__VALUE__) == LL_GPIO_MODE_OUTPUT) || ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) || ((__VALUE__) == LL_GPIO_MODE_ANALOG))LL_GPIO_DeInit/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/STM32CubeF2/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_gpio.cGNU C17 13.3.1 20240614 -mthumb -mfloat-abi=soft -mcpu=cortex-m3 -march=armv7-m -ggdb3 -O3 -ffreestanding -fbuiltin -flto -fno-fat-lto-objectsLL_GPIO_SetPinSpeedIS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) || ((__VALUE__) == LL_GPIO_PULL_UP) || ((__VALUE__) == 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(uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))LL_RCC_PLL_IsReadyLL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000ULL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0)LL_RCC_GetSysClkSourceEXTERNAL_CLOCK_VALUE 12288000ULL_RCC_CIR_HSERDYC RCC_CIR_HSERDYCSYSCLK_FrequencyLL_RCC_HSI_SetCalibTrimmingLL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)LL_RCC_GetAPB2PrescalerLL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTFPCLK2_FrequencyLL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0LL_RCC_PLLI2S_IsReadyLL_RCC_GetAPB1PrescalerLL_RCC_WriteReg(__REG__,__VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1vl_maskLSI_VALUE 32000ULL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4)LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)RCC_PLL_GetFreqDomain_48MLL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0)LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYCLL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIELL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4)LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/STM32CubeF2/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_rcc.cLL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1)LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64pllsourceRCC_PLLI2S_GetFreqDomain_I2SLL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYFLL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLLLL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)LL_RCC_PLL_GetMainSourceLL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSELL_RCC_CSR_PINRSTF RCC_CSR_PINRSTFLL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)HSI_VALUE 16000000ULL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)RCC_GetHCLKClockFreqLL_RCC_PLL_GetDividerLL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSILL_RCC_CIR_LSERDYC RCC_CIR_LSERDYCLL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)__LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__,__APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))RCC_ClocksHCLK_FrequencyLL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3)LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTFLL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIELL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYFLL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128LL_RCC_GetSystemClocksFreqLL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1)LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1LL_RCC_ClocksTypeDefLL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)LL_RCC_PLLQ_DIV_10 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(uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))LL_RCC_PLL_GetPRCC_GetPCLK2ClockFreqLL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIELL_RCC_SPREAD_SELECT_CENTER 0x00000000ULL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)RCC_PLL_GetFreqDomain_SYSLL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1__LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__,__PLLM__,__PLLN__,__PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))LL_RCC_GetI2SClockSourceRCC_GetPCLK1ClockFreq__LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__,__APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSILL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5)LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512LL_RCC_RTC_HSE_DIV_19 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RCC_PLLCFGR_PLLM_2)LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYFLL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSELL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIELL_RCC_GetI2SClockFreqLL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U__STM32F2xx_LL_RCC_H LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2)LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))LL_RCC_PLL_GetNLL_RCC_PLL_GetQLL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))AHBPrescTableLL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)LL_RCC_HSI_EnableLL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4LL_RCC_RTC_NOCLOCK 0x00000000ULL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1)LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2)LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)LSE_VALUE 32768ULL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSELL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0)LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1)LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)pllinputfreqLL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSILL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)LL_RCC_CIR_CSSF RCC_CIR_CSSFLL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)I2SxLL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTFtmpsmcrLL_TIM_HALLSENSOR_InitTypeDefCommutationDelayIS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))LL_TIM_HALLSENSOR_StructInitOC4ConfigIS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) || ((__VALUE__) == LL_TIM_OSSR_ENABLE))IC1FilterIS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))OCNIdleStateCompareValueLL_TIM_SetEncoderModeLL_TIM_StructInitOCNPolarityIC1ConfigLL_TIM_ENCODER_InitICPrescalerLL_TIM_SetPrescalerIS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) || ((__VALUE__) == LL_TIM_OSSI_ENABLE))LL_TIM_ENCODER_StructInitDeadTimeOC2ConfigIC3ConfigLL_TIM_IC_StructInitLL_TIM_OC_InitICActiveInputLL_TIM_BDTR_StructInitLL_TIM_OC_StructInitLL_TIM_ENCODER_InitTypeDeftmpcr1OCStatetmpccmr1tmpccmr2OCIdleStateIS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))LL_TIM_OC_SetCompareCH2OCModeIS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))OCNStateIC2PrescalerIS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) || ((__VALUE__) == LL_TIM_OCMODE_PWM1) || ((__VALUE__) == LL_TIM_OCMODE_PWM2))LockLevelIS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) || ((__VALUE__) == LL_TIM_ICPSC_DIV2) || ((__VALUE__) == LL_TIM_ICPSC_DIV4) || ((__VALUE__) == LL_TIM_ICPSC_DIV8))IC1PrescalerIS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))IC2FilterIC1ActiveInputTIM_IC_InitStructBreakStateIS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))ICFilterIC4ConfigIC2ConfigTIM_BDTRInitStructLL_TIM_HALLSENSOR_InitLL_TIM_OC_SetCompareCH1LL_TIM_OC_SetCompareCH3LL_TIM_OC_SetCompareCH4TIM_InitStructOCPolarityOC3ConfigIS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))tmpbdtrIS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))tmpccerIC2ActiveInput/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/STM32CubeF2/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_tim.cLL_TIM_DeInitLL_TIM_IC_InitIC2PolarityLL_TIM_BDTR_InitTypeDefTIM_OC_InitStructTIM_ICInitStructIS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))ICPolarityOSSRStateOC1ConfigLL_TIM_IC_InitTypeDefBreakPolarityTIM_OCInitStructLL_TIM_BDTR_InitAutomaticOutputOSSIStateIS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) || ((__VALUE__) == LL_TIM_BREAK_ENABLE))TIM_EncoderInitStructLL_APB1_GRP1_ReleaseResetLL_TIM_GenerateEvent_UPDATELL_TIM_SetRepetitionCounterLL_APB1_GRP1_ForceResetTIM_HallSensorInitStructtmpcr2IC1Polarity__LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__,__BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))__LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__,__BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)__LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__,__BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)LL_USART_HWCONTROL_NONE 0x00000000UDataWidth__LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__,__BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))LL_USART_SR_PE USART_SR_PE/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/STM32CubeF2/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usart.cLL_USART_IsEnabledLL_USART_CR3_CTSIE USART_CR3_CTSIELL_USART_POLARITY_HIGH USART_CR2_CPOLClockOutput__LL_USART_DIV_SAMPLING16(__PERIPHCLK__,__BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)LL_USART_LINBREAK_DETECT_10B 0x00000000ULL_USART_PHASE_2EDGE USART_CR2_CPHALL_USART_SR_ORE USART_SR_ORELL_USART_StructInitIS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)LL_USART_ClockInitLL_USART_CR1_TXEIE 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0x00000000ULL_USART_CR1_RXNEIE USART_CR1_RXNEIEperiphclkLL_USART_SR_TC USART_SR_TCLL_USART_SetBaudRateIS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) || ((__VALUE__) == LL_USART_HWCONTROL_RTS) || ((__VALUE__) == LL_USART_HWCONTROL_CTS) || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))LL_USART_HWCONTROL_RTS USART_CR3_RTSELL_USART_SR_IDLE USART_SR_IDLELL_USART_DATAWIDTH_8B 0x00000000ULL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)__LL_USART_DIV_SAMPLING8(__PERIPHCLK__,__BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))LL_USART_DIRECTION_NONE 0x00000000UClockPolarityLL_USART_SR_RXNE USART_SR_RXNELL_USART_DIRECTION_RX USART_CR1_REIS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) || ((__VALUE__) == LL_USART_CLOCK_ENABLE))LL_USART_CLOCK_ENABLE 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60000000ULL_SetFlashLatencyUTILS_LATENCY1_FREQ 30000000UIS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) || ((__VALUE__) == LL_RCC_PLLM_DIV_3) || ((__VALUE__) == LL_RCC_PLLM_DIV_4) || ((__VALUE__) == LL_RCC_PLLM_DIV_5) || ((__VALUE__) == LL_RCC_PLLM_DIV_6) || ((__VALUE__) == LL_RCC_PLLM_DIV_7) || ((__VALUE__) == LL_RCC_PLLM_DIV_8) || ((__VALUE__) == LL_RCC_PLLM_DIV_9) || ((__VALUE__) == LL_RCC_PLLM_DIV_10) || ((__VALUE__) == LL_RCC_PLLM_DIV_11) || ((__VALUE__) == LL_RCC_PLLM_DIV_12) || ((__VALUE__) == LL_RCC_PLLM_DIV_13) || ((__VALUE__) == LL_RCC_PLLM_DIV_14) || ((__VALUE__) == LL_RCC_PLLM_DIV_15) || ((__VALUE__) == LL_RCC_PLLM_DIV_16) || ((__VALUE__) == LL_RCC_PLLM_DIV_17) || ((__VALUE__) == LL_RCC_PLLM_DIV_18) || ((__VALUE__) == LL_RCC_PLLM_DIV_19) || ((__VALUE__) == LL_RCC_PLLM_DIV_20) || ((__VALUE__) == LL_RCC_PLLM_DIV_21) || ((__VALUE__) == LL_RCC_PLLM_DIV_22) || ((__VALUE__) == LL_RCC_PLLM_DIV_23) || ((__VALUE__) == LL_RCC_PLLM_DIV_24) || ((__VALUE__) == LL_RCC_PLLM_DIV_25) || ((__VALUE__) == LL_RCC_PLLM_DIV_26) || ((__VALUE__) == LL_RCC_PLLM_DIV_27) || ((__VALUE__) == LL_RCC_PLLM_DIV_28) || ((__VALUE__) == LL_RCC_PLLM_DIV_29) || ((__VALUE__) == LL_RCC_PLLM_DIV_30) || ((__VALUE__) == LL_RCC_PLLM_DIV_31) || ((__VALUE__) == LL_RCC_PLLM_DIV_32) || ((__VALUE__) == LL_RCC_PLLM_DIV_33) || ((__VALUE__) == LL_RCC_PLLM_DIV_34) || ((__VALUE__) == LL_RCC_PLLM_DIV_35) || ((__VALUE__) == LL_RCC_PLLM_DIV_36) || ((__VALUE__) == LL_RCC_PLLM_DIV_37) || ((__VALUE__) == LL_RCC_PLLM_DIV_38) || ((__VALUE__) == LL_RCC_PLLM_DIV_39) || ((__VALUE__) == LL_RCC_PLLM_DIV_40) || ((__VALUE__) == LL_RCC_PLLM_DIV_41) || ((__VALUE__) == LL_RCC_PLLM_DIV_42) || ((__VALUE__) == LL_RCC_PLLM_DIV_43) || ((__VALUE__) == LL_RCC_PLLM_DIV_44) || ((__VALUE__) == LL_RCC_PLLM_DIV_45) || ((__VALUE__) == LL_RCC_PLLM_DIV_46) || ((__VALUE__) == LL_RCC_PLLM_DIV_47) || ((__VALUE__) == LL_RCC_PLLM_DIV_48) || ((__VALUE__) == LL_RCC_PLLM_DIV_49) || ((__VALUE__) == LL_RCC_PLLM_DIV_50) || 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pxHigherPriorityTaskWoken )vTaskRemoveFromUnorderedEventListxTimerDelete(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )TIMERS_H xTimerStopFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )strtodf strtof__restrict_arr restrictEVENT_GROUPS_H eventEVENT_BITS_CONTROL_BYTES 0xff000000ULxTimerResetFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )pxListItemEXIT_FAILURE 1xWaitConditionMetxEventGroupWaitBitseventWAIT_FOR_ALL_BITS 0x04000000ULxItemValuexEventGroupCreateStaticpxItemvListInsertEndpxItemToRemovepxIteratorpxNewListItemxValueOfInsertionvListInitialiseItemvListInsertuxListRemove/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/FreeRTOS/list.cqueueUNLOCKED ( ( int8_t ) -1 )queueQUEUE_IS_MUTEX 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xTaskResumeAll();xTaskGenericNotifyWaitprvWriteMessageToBufferxFirstLengthxTaskWaitingToSendxShouldWritexReceivedLengthxHeadxStreamBufferGenericCreateStaticxOriginalTailxStreamBufferReceiveeSetValueWithoutOverwriteprvInitialiseNewStreamBufferxWriteValuepvRxDatauxDummy1xStreamBufferNextMessageLengthBytesprvBytesInBuffer/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/FreeRTOS/stream_buffer.cxNextHeadxStreamBufferSendCompletedFromISRsbRECEIVE_COMPLETED_FROM_ISR(pxStreamBuffer,pxHigherPriorityTaskWoken) { UBaseType_t uxSavedInterruptStatus; uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); { if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) { ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, ( uint32_t ) 0, eNoAction, pxHigherPriorityTaskWoken ); ( pxStreamBuffer )->xTaskWaitingToSend = NULL; } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); }pucStreamBufferStorageAreaxTriggerLevelBytesxSpacexNextTailvTaskSetTimeOutStatexStreamBufferIsFullsbSEND_COMPLETED(pxStreamBuffer) vTaskSuspendAll(); { if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) { ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, ( uint32_t ) 0, eNoAction ); ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; } } ( void ) xTaskResumeAll();ucFlagsxStreamBufferReceiveCompletedFromISRpxStreamBuffereIncrementxStreamBufferSendFromISRprvWriteBytesToBufferxTaskWaitingToReceivepucBufferStreamBufferHandle_txTailxTaskGenericNotifyFromISRsbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )xTaskGenericNotifyStateClearprvReadMessageFromBuffereSetValueWithOverwritexStreamBufferIsEmptyxTriggerLevelxStreamBufferSpacesAvailablesbSEND_COMPLETE_FROM_ISR(pxStreamBuffer,pxHigherPriorityTaskWoken) { UBaseType_t uxSavedInterruptStatus; uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); { if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) { ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, ( uint32_t ) 0, eNoAction, pxHigherPriorityTaskWoken ); ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); }ucDummy3xStreamBufferSetTriggerLevelvStreamBufferDeletesbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 )StreamBufferDef_tpxStaticStreamBufferxSTATIC_STREAM_BUFFERpvTxDataxStreamBufferSendeNoActionxBufferSizeBytesxTaskToNotifyvPortEndSchedulerxCanBlockIndefinitelypxOverflowDelayedTaskListvTaskEndScheduleruxHighestPriorityWaitingTaskuxTaskPriorityGettaskSELECT_HIGHEST_PRIORITY_TASK() { UBaseType_t uxTopPriority; portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); }ucOriginalNotifyStatexRegionsxTicksToCatchUpxTaskToSuspendxDelayedTaskList2uxIndexToWaitpxTimeOutvTaskSuspendprvCheckTasksWaitingTerminationtskSET_NEW_STACKS_TO_KNOWN_VALUE 0taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 )xClearCountOnExitvPortRaiseBASEPRItskTCBulStackDepthuxOnlyOneMutexHeldpxUnblockedTCBeActionulLengthInBytesuxPriorityToUsexYieldPendingxTimeToWakeuxCurrentBasePriorityucNotifyStateulReturntaskWAITING_NOTIFICATION ( ( uint8_t ) 1 )taskRESET_READY_PRIORITY(uxPriority) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) { portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); } }ulBitsToClearOnExitpxReadyTasksListsvTaskDelayprvInitialiseTaskListsprvTaskIsTaskSuspendedxTaskCreateStaticprvDeleteTCBulParameterstskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 )uxNewPriorityuxSavedInterruptStatepxCurrentTCBvTaskDeletetaskCHECK_FOR_STACK_OVERFLOW() { if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) { vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); } }uxIndexToClearuxCurrentNumberOfTasksxPortStartSchedulertskRUNNING_CHAR ( 'X' )ulNotifiedValuevApplicationGetIdleTaskMemoryxStateListItemtskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 )prvResetNextTaskUnblockTimepxMutexHolderTCBprvGetTCBFromHandle(pxHandle) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )pxTaskBufferxTaskCatchUpTicksuxTaskNumberxTicksxTaskToDeleteuxSchedulerSuspendedpxStackprvIdleTaskuxPriorityvTaskPrioritySettskDELETED_CHAR ( 'D' )xTaskToResumexElapsedTimeprvInitialiseNewTaskuxTaskPriorityGetFromISRuxTaskGetNumberOfTasksulTaskGenericNotifyValueClearuxIndexToNotifypxDelayedTaskListulBitmaptskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 )TCB_tulValuepxTicksToWaitxTaskGetTickCountpulPreviousNotificationValuexTaskIncrementTickpxTaskCodexTaskToQuerytaskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000ULuxPriorityUsedOnEntrypvParametersprvAddNewTaskToReadyListpxMutexHolderpxTempuxTopReadyPrioritypcTaskNameprvAddTaskToReadyList(pxTCB) traceMOVED_TASK_TO_READY_STATE( pxTCB ); taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )vTaskStartSchedulerxTasksWaitingTerminationpuxStackBufferxPendingReadyListvTaskGenericNotifyGiveFromISRtskBLOCKED_CHAR ( 'B' )xSwitchRequiredvTaskResumexTaskGetTickCountFromISRucPortCountLeadingZerosxYieldOccurredxTicksToDelaytaskSWITCH_DELAYED_LISTS() { List_t * pxTemp; configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); pxTemp = pxDelayedTaskList; pxDelayedTaskList = pxOverflowDelayedTaskList; pxOverflowDelayedTaskList = pxTemp; xNumOfOverflows++; prvResetNextTaskUnblockTime(); }xTaskpcNametskREADY_CHAR ( 'R' )pulNotificationValuevTaskSwitchContextpxCreatedTaskpxNewTCBvApplicationStackOverflowHookuxTopPriorityxPendedTickspxPortInitialiseStackxConstTickCountpxEventListxTaskResumeFromISRconfigIDLE_TASK_NAME "IDLE"pxTopOfStackucReturnuxBasePrioritytaskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 )xNumOfOverflowsxIdleTaskHandleulBitsToClearOnEntryxMEMORY_REGIONtskSTACK_FILL_BYTE ( 0xa5U )xSchedulerRunningxTickCounttaskRECORD_READY_PRIORITY(uxPriority) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )xNextTaskUnblockTimepxConstListpvBaseAddress/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/FreeRTOS/tasks.cSTACK_MACROS_H xPendedCountsulTaskGenericNotifyTaketskSUSPENDED_CHAR ( 'S' )prvAddCurrentTaskToDelayedListtaskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()uxMutexesHeldxSuspendedTaskListxDelayedTaskList1pxEventListItemuxDeletedTasksWaitingCleanUppcInterruptPriorityRegistersucCurrentPriorityportMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )portMISSED_COUNTS_FACTOR ( 45UL )portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZportNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )ucMaxSysCallPriorityulCurrentInterruptxPortSysTickHandlerportNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )portINITIAL_XPSR ( 0x01000000UL )portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )portMAX_24_BIT_NUMBER ( 0xffffffUL )ulOriginalPriorityucMaxPriorityValueulDummy/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/vendor/FreeRTOS/portable/GCC/ARM_CM3/port.cportNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )vPortSetupTimerInterruptportNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )uxCriticalNestingportPRIORITY_GROUP_MASK ( 0x07UL << 8UL )prvPortStartFirstTaskpucFirstUserPriorityRegisterportNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )pxCodeulMaxPRIGROUPValueportFIRST_USER_INTERRUPT_NUMBER ( 16 )portPRIGROUP_SHIFT ( 8UL )portTASK_RETURN_ADDRESS prvTaskExitErrorportVECTACTIVE_MASK ( 0xFFUL )LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)LL_RTC_ISR_WUTF RTC_ISR_WUTFLL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)LL_RTC_BKP_DR7 0x00000007Ubootcmd_initLL_RTC_WriteReg(__INSTANCE__,__REG__,__VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4RTC_INIT_MASK 0xFFFFFFFFULL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)bootcmd_get_silentLL_RTC_MONTH_JULY ((uint8_t)0x07U)__STM32F2xx_LL_PWR_H LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000ULL_RTC_ALMB_TIME_FORMAT_AM 0x00000000ULL_RTC_ISR_ALRAF RTC_ISR_ALRAFLL_RTC_CR_WUTIE RTC_CR_WUTIELL_RTC_CR_ALRBIE RTC_CR_ALRBIELL_RTC_MONTH_AUGUST ((uint8_t)0x08U)LL_RTC_BKP_DR17 0x00000011ULL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)bootcmd_get_cmdRTC_OFFSET_MINUTE 8ULL_RTC_ALMA_MASK_NONE 0x00000000ULL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)LL_RTC_ISR_ALRBF RTC_ISR_ALRBFLL_RTC_BAK_GetRegisterLL_RTC_MONTH_OCTOBER ((uint8_t)0x10U)LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1LL_RTC_BKP_DR0 0x00000000ULL_PWR_MODE_STANDBY (PWR_CR_PDDS)LL_PWR_CR_CSBF PWR_CR_CSBFLL_RTC_ISR_RSF RTC_ISR_RSFLL_RTC_ALARMOUT_WAKEUP RTC_CR_OSELLL_RCC_EnableRTCLL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0)LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4LL_RTC_TamperPin_Pos1 RTC_TAFCR_TAMP1INSELLL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL_bootcmd_t__STM32F2xx_LL_RTC_H LL_RTC_CALIB_PERIOD_32SEC 0x00000000URTCxbootcmd_get_bl_revisionLL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)__LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)LL_RTC_CR_TSIE RTC_CR_TSIELL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)RTC_OFFSET_DAY 16ULL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1)LL_RTC_BKP_DR4 0x00000004ULL_RTC_MONTH_DECEMBER ((uint8_t)0x12U)LL_RTC_BKP_DR2 0x00000002ULL_RTC_ISR_TAMP2F RTC_ISR_TAMP2FLL_RTC_ISR_TSOVF RTC_ISR_TSOVFLL_RTC_BKP_DR12 0x0000000CULL_RTC_ALARMOUT_DISABLE 0x00000000U__NO_MATH_ERRNO__ 1LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWFLL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PMLL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MFLL_RTC_BKP_DR5 0x00000005U__LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)LL_RTC_ISR_SHPF RTC_ISR_SHPFBOOTCMD_NEW_LOADERLL_RTC_ISR_WUTWF RTC_ISR_WUTWFRTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)RTC_OFFSET_MONTH 8ULL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)LL_RTC_BKP_DR8 0x00000008ULL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)LL_RTC_BKP_DR10 0x0000000AULL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPELL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)RTC_RSF_MASK 0xFFFFFF5FULL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)LL_RTC_TS_TIME_FORMAT_AM 0x00000000U__LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3Fbootcmd_service_updateLL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)LL_RTC_MONTH_JUNE ((uint8_t)0x06U)__NO_TRAPPING_MATH__ 1LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2)LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE)LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1LL_RTC_HOURFORMAT_24HOUR 0x00000000ULL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIELL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)LL_RTC_BAK_SetRegisterLL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U)LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)LL_RTC_ALMB_MASK_NONE 0x00000000ULL_PWR_EnableBkUpAccessLL_PWR_CSR_EWUP1 PWR_CSR_EWUPbootcmd_set_silentLL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)LL_RTC_ISR_INITS RTC_ISR_INITSLL_RTC_BKP_DR18 0x00000012ULL_RTC_ALMA_TIME_FORMAT_AM 0x00000000ULL_RTC_CALIB_SIGN_NEGATIVE RTC_CALIBR_DCS__LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))__ASSOCIATIVE_MATH__ 1LL_APB1_GRP1_EnableClockLL_PWR_REGU_DSMODE_MAIN 0x00000000ULL_RTC_MONTH_MARCH ((uint8_t)0x03U)LL_RTC_BKP_DR15 0x0000000FULL_PWR_CSR_PVDO PWR_CSR_PVDOLL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL__GNUC_EXECUTION_CHARSET_NAME "cp1252"LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)BOOTCMD_UPDATELL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PMLL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)LL_PWR_MODE_STOP_MAINREGU 0x00000000ULL_RTC_ISR_INITF RTC_ISR_INITFLL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASELL_RTC_WAKEUPCLOCK_DIV_16 0x00000000UBackupRegister__LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)LL_RTC_BKP_DR9 0x00000009ULL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALPLL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000ULL_PWR_CSR_SBF PWR_CSR_SBFLL_RTC_ISR_TSF RTC_ISR_TSFLL_RTC_BKP_DR13 0x0000000DUGNU C17 13.3.1 20240614 -mthumb -mfloat-abi=soft -mcpu=cortex-m3 -march=armv7-m -ggdb3 -O3 -O3 -ffreestanding -fbuiltin -flto -fno-fat-lto-objects -ffast-math -fexec-charset=cp1252RTC_OFFSET_HOUR 16ULL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1MSIGN_GIT_REV "-broken-eap-sm-reinit-c9fb179"BOOTCMD_H LL_RTC_MONTH_MAY ((uint8_t)0x05U)LL_RTC_CALIB_SIGN_POSITIVE 0x00000000ULL_RTC_BKP_DR6 0x00000006U/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/common/bootcmd.cPWR_TypeDefLL_PWR_WriteReg(__REG__,__VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PMLL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGEbootcmd_did_just_update__LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)__NO_SIGNED_ZEROS__ 1__FAST_MATH__ 1LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U)__LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16BOOTCMD_RUNLL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)LL_RTC_CR_ALRAIE RTC_CR_ALRAIELL_RTC_BKP_DR11 0x0000000BU__LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)LL_RTC_BKP_DR16 0x00000010ULL_PWR_CSR_WUF PWR_CSR_WUFLL_RTC_TamperPin_Default 0x00000000ULL_RTC_MONTH_JANUARY ((uint8_t)0x01U)RTC_OFFSET_WEEKDAY 24URTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)LL_RTC_TIME_FORMAT_PM RTC_TR_PMLL_RTC_BKP_DR19 0x00000013ULL_RTC_CALIB_INSERTPULSE_NONE 0x00000000ULL_RTC_MONTH_APRIL ((uint8_t)0x04U)LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8LL_RTC_BKP_DR3 0x00000003ULL_RTC_FORMAT_BCD 0x000000001ULL_RTC_ISR_ALRAWF RTC_ISR_ALRAWFLL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)__RECIPROCAL_MATH__ 1LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000ULL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000ULL_RTC_FORMAT_BIN 0x000000000ULL_RTC_TAMPER_1 RTC_TAFCR_TAMP1Ebootcmd_update_sizeLL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000ULL_RTC_CALIB_OUTPUT_NONE 0x00000000ULL_PWR_CR_CWUF PWR_CR_CWUFLL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP)LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)bootcmd_request_update__LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)LL_RTC_TimeStampPin_Default 0x00000000ULL_RTC_HOURFORMAT_AMPM RTC_CR_FMTLL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSELLL_RTC_DisableWriteProtectionLL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1FLL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRGLL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)LL_RTC_ReadReg(__INSTANCE__,__REG__) READ_REG(__INSTANCE__->__REG__)LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)LL_RTC_TimeStampPin_Pos1 RTC_TAFCR_TSINSELLL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U__FINITE_MATH_ONLY__ 1LL_RTC_BKP_DR1 0x00000001ULL_RTC_BKP_DR14 0x0000000EU_ZN4util9crc_validEPhjcrc_validMSN_UTIL_H GNU C++20 13.3.1 20240614 -mthumb -mfloat-abi=soft -mcpu=cortex-m3 -march=armv7-m -ggdb3 -O3 -O3 -std=gnu++20 -ffreestanding -fbuiltin -fno-exceptions -fno-rtti -flto -fno-fat-lto-objects -ffast-math -fexec-charset=cp1252 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66>freezing_rainlookup_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEcvS8_Ev_ZN3srv8Servicer19immediately_processEvimmediately_processcheck_connection_pingcurrsize_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE10invalidateINS4_8IteratorINS_5BlockELb1EEEEEvT_S9__ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEC2ERS6__ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEEC4EvRESEND_LAST_CHUNK_CSUM_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEEC2Evmsgbufcontainspoll_another_pr_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEC4Evfreedupdate_tempflash_sector_countertarget_locAdjacent_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3endEvtotalbegin_region_ZNK3srv8Servicer7crashedEvbcache_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEC4ERS7_operator()inner_offmiddle_start_ZNK3srv8Servicer8updatingEvsuboffsetFLASH_KEY2 0xCDEF89ABU__find_if >::Iterator, __gnu_cxx::__ops::_Iter_pred > >update_checksumget_debug_information_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE4lastEmbucket_for_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEC4ERS7_PREPARE_FOR_IMAGE_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEC2Ev_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEeqERKS7__ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEC2Ev_ZN3srv8Servicer20wait_for_not_sendingEvsendoffsetUSTATE_WAITING_FOR_FINISH 12is_startconstant__active_request_send_retries_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEptEvoperator() >::Iterator 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0_ZSt3minIjERKT_S2_S2_subcmd_ZN3lru5CacheILj16ELj4EE5evictEt_ZN3srv8Servicer23update_append_data_copyEvputmove_update_errcodeupdate_tempflash_data_ptris_endnew_lengthsend_data_requestsfinish_setting_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEC2ERS7__ZN3srv8Servicer11is_sleepingEvArena_ZN3srv8Servicer13update_statusEvend_temp_requestUSTATE_ERASING_BEFORE_IMAGE 1scratch_area_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3getEmlog_in_private_ZN5slots13PacketWrapperILh0EE3putItEEvT_h_ZNK3lru5CacheILj16ELj4EE8containsEtNotEnoughSpace_TryAgain_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEC2ERS7_/home/jenkins/workspace/SignCode_broken-eap-sm-reinit/stm/src/srv.cppCOPY_COMPLETEDABORT_CSUM_ZNK3lru5CacheILj16ELj4EE10bucket_forEt_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEptEvupdate_statedma_rx_queue_data_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE15update_contentsIZNS4_15update_contentsEmmmPKvbEUlmmS7_E_EENSt9enable_ifIX16is_invocable_r_vIbT_mmS7_EEbE4typeEmmmS7_OSA_blog_outendptrpending_requests_datamoved_sizeUSTATE_ERASING_BEFORE_PACKET 4_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE10free_spaceEm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEcvNS5_IKS6_Lb1EEEEv_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE4lastEm_ZN3lru5CacheILj16ELj4EEC2Ev_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE11split_blockERNS_5BlockEmenable_ifInvalidOrNak_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEppEv_ZN3srv8Servicer16try_cleanup_heapEibegin_updatetime_when_sentnext_empty_Iter_pred >sublengthupdate_contents >::update_contents(uint32_t, uint32_t, uint32_t, void const*, bool):: >try_cleanup_heapnonadj_iterator_ZSt3maxIjERKT_S2_S2__ZN5slots13PacketWrapperILh0EE3putINS_8protocol14AdcCalibrationEEEvT_hlast_emptyticks_since_last_communicationmin_Iter_predmsgbuf_x16process_update_packetscratch_sizeupdate_pkg_bufferalready_erasedretry_handshakeIteratorbegin_location_ZSt4swapImENSt9enable_ifIXsrSt6__and_IJSt6__not_ISt15__is_tuple_likeIT_EESt21is_move_constructibleIS4_ESt18is_move_assignableIS4_EEE5valueEvE4typeERS4_SE__ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEcvNS5_IKS6_Lb0EEEEv_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE10free_spaceERKNS_5BlockEminvalidatedwait_for_update_status_onscreendatalocation_ZZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE15update_contentsEmmmPKvbENKUlmmS6_E_clEmmS6_get_from_cache_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEC4EvERR_IMG_READping_is_in_flightUpdateCmdREADY_FOR_CHUNKorig_offsetupdate_append_dataoperator bheap::Arena<13312, lru::Cache<16, 4> >::Iterator_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEneERKS7_set_locationupdate_tempflash_data_counterevict_ifBEGINNING_COPY_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE10homogenizeEmshift_requiredin_front_oftarget_area_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEdeEvUPDATE_COMPLETED_OK_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEcvPS7_Ev_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3getEmmrepeatloopoffset_in_blockmove_leftinner_begin_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEneERKS8_pending_requests_private_ZN3srv8Servicer18send_data_requestsEvlast_slotid_ZN3srv8Servicer21update_status_versionEv_ZN3srv8Servicer5readyEv_ZZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3getEmENUlvE_D4Evcurrent_spacespace_requiredsyncoperator bheap::Arena<13312, lru::Cache<16, 4> >::IteratorREADY_FOR_IMAGEhandshake_statecalib_out_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE19ensure_single_blockEmmmshould_reclaim_ZN3srv8Servicer9write_dbgEPhjmbcheck_locationsids_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEppEi_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE4cendEm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE4cendEvwait_for_not_sendingoperator++begin_posUpdateStatus_ZN3lru5CacheILj16ELj4EE8evict_ifEttadd_block_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEC2Ev_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEeqERKS7__ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE6cachedEmmaxupdate_append_data_copylog_in_data_ZN3srv8Servicer12begin_updateEv_ZN3srv8Servicer18start_pend_requestERNS0_11PendRequestELL_FLASH_DisableDataCacheReset_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE13contents_sizeEmpaste_to_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEptEv_ZN3srv8Servicer19set_adc_calibrationERKN5slots8protocol14AdcCalibrationE_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEppEvstarting_posold_emptyDataStoreFulfillResultensure_single_blockresponse_ZN3lru5CacheILj16ELj4EEC4Evhdramount_ZN3srv8Servicer15do_update_logicEvUSTATE_WAITING_FOR_PACKET 2defragfree_spaceERR_IMG_CSUMfree_space_cleanup_arenanew_containset_sleep_mode_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE6cbeginEm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE6cbeginEv_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE12block_offsetERKNS_5BlockE_ZN3srv8Servicer31wait_for_update_status_onscreenEvlast_slotid_tries_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3endEm_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3endEv_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3getEmmLL_FLASH_EnableDataCacheResetblock_offset_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE15set_temperatureEmmis_dirty_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEEixEm_ZZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE15update_contentsEmmmPKvbENUlmmS6_E_D4Ev_ZN3lru5CacheILj16ELj4EE6insertEttUSTATE_FAILED 10ESP_WROTE_SECTOR_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE12set_locationEmmmm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEcvPS6_Ev_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEeqERKS8__ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE17truncate_contentsEmmupdate_contentslog_out_privatetotal_reclaimedto_moveput_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8containsEmany_of >::Iterator, srv::Servicer::slot_dirty(uint16_t, bool):: >_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEC4Evstart_pend_requestnone_of >::Iterator, srv::Servicer::slot_dirty(uint16_t, bool):: >update_chunks_remainingswap_ZN3lru5CacheILj16ELj4EE5evictEv_ZN3srv8Servicer5arenaEread_dbg_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEptEvUSTATE_PACKET_WRITTEN 3write_dbgIteratorIllegalStateoperator bheap::Block*can_interrupt_with_notification_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE14check_locationEmmmmshould_end_atFLASH_KEY1 0x45670123UPROTOCOL_ERRORdo_handshakemark_dirty_ZN3srv8Servicer5resetEvtruncate_contentsremaining_new_alloc_spaceerase_flash_sectorfind_if >::Iterator, srv::Servicer::slot_dirty(uint16_t, bool):: >middle_endinner_end_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE15update_contentsEmmmPKvbERR_STATUSto_free_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE3getEm_ZN3srv8Servicer18send_update_statusEN5slots8protocol12UpdateStatusE_ZN3lru5CacheILj16ELj4EE6lookupEt_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE9add_blockEmmj_ZN3srv8Servicer8read_dbgEPhjm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEcvS8_Evpacket_lengthfree_space_arena_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE9move_leftERNS_5BlockES6_total_upd_lennewsize_ZN3srv8Servicer14set_sleep_modeEb_ZN3srv8Servicer24needs_temperature_updateEttprocess_update_cmd_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEEixEmUSTATE_SEND_READY 20split_block_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE10invalidateEPKNS_5BlockE_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEC2Ev_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE5beginEm_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE5beginEvmake_space_afterpaste_amountupdate_status_versioninvalidate_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE13bptr_to_cacheEPKNS_5BlockE_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb1EEC4Ev_ZNK3lru5CacheILj16ELj4EE6lookupEt_ZN3lru5CacheILj16ELj4EE19lookup_or_calculateIZN5bheap5ArenaILj13312ES1_E3getEmEUlvE_EEttOT_StaticSemaphore_tnew_emptyreference_ZN3srv8Servicer21get_debug_informationEvcontents_size_ZN3srv8Servicer12request_timeERyS1_lookup_or_calculate >::get(uint32_t):: >is_in_sleep_modeupdate_pkg_size_ZN3srv8Servicer18update_append_dataEbArena<13312, lru::Cache<16, 4> >reclaimable_spacesend_update_statusCANCEL_UPDATERemoteHandlercontaining_block_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEdeEvsid_frameDebugInfo_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEC2ERS6_USTATE_WAITING_FOR_FINISH_WRITE 22_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEC4ERS6_newbSKIP_STM_UPDATElog_inbptr_to_cache_ZN3srv8Servicer12do_handshakeEv_M_pred_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEppEi_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEppEvCache<16, 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11USTATE_WAITING_FOR_FINISH_SECTORCOUNT 21_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEppEi_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb1EEppEvupdate_status_cookie_ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorIKNS_5BlockELb0EEneERKS8__ZNK5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE8IteratorINS_5BlockELb0EEcvPS6_Ev_ZN5bheap5ArenaILj13312EN3lru5CacheILj16ELj4EEEE14get_from_cacheEtrequest_timeinvalidate >::Iterator >operator const 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